Lines Matching refs:cmac
85 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
91 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
98 static int pm3393_reset(struct cmac *cmac)
111 static int pm3393_interrupt_enable(struct cmac *cmac)
117 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
118 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
119 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
120 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
123 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
124 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
125 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
126 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
128 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
129 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
130 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
131 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
132 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
133 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
134 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
135 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
136 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
141 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
145 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
147 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
151 static int pm3393_interrupt_disable(struct cmac *cmac)
156 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
157 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
158 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
159 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
160 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
161 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
162 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
163 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
164 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
165 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
166 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
167 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
168 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
169 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
170 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
171 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
172 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
175 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
178 t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
180 t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
190 static int pm3393_interrupt_clear(struct cmac *cmac)
199 pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
200 pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
201 pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
202 pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
203 pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
204 pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
205 pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
206 pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
207 pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
208 pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
209 pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
210 pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
212 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
213 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
217 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
221 t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
223 t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
227 pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
229 writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
235 static int pm3393_interrupt_handler(struct cmac *cmac)
240 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
242 if (netif_msg_intr(cmac->adapter))
243 dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n",
247 pm3393_interrupt_clear(cmac);
252 static int pm3393_enable(struct cmac *cmac, int which)
255 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
261 if (cmac->instance->fc & PAUSE_RX)
263 if (cmac->instance->fc & PAUSE_TX)
265 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
268 cmac->instance->enabled |= which;
272 static int pm3393_enable_port(struct cmac *cmac, int which)
275 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
278 memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
280 pm3393_enable(cmac, which);
287 t1_link_changed(cmac->adapter, 0);
291 static int pm3393_disable(struct cmac *cmac, int which)
294 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
296 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
304 cmac->instance->enabled &= ~which;
308 static int pm3393_loopback_enable(struct cmac *cmac)
313 static int pm3393_loopback_disable(struct cmac *cmac)
318 static int pm3393_set_mtu(struct cmac *cmac, int mtu)
320 int enabled = cmac->instance->enabled;
326 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
328 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
329 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
332 pm3393_enable(cmac, enabled);
336 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
338 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
343 pm3393_disable(cmac, MAC_DIRECTION_RX);
345 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
348 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
357 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
358 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
359 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
360 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
373 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
374 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
375 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
376 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
380 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
383 pm3393_enable(cmac, MAC_DIRECTION_RX);
388 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
396 *fc = cmac->instance->fc;
400 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
410 if (fc != cmac->instance->fc) {
411 cmac->instance->fc = (u8) fc;
412 if (cmac->instance->enabled & MAC_DIRECTION_TX)
413 pm3393_enable(cmac, MAC_DIRECTION_TX);
433 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
484 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
486 memcpy(mac_addr, cmac->instance->mac_addr, ETH_ALEN);
490 static int pm3393_macaddress_set(struct cmac *cmac, const u8 ma[6])
492 u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
513 memcpy(cmac->instance->mac_addr, ma, ETH_ALEN);
521 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
524 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
525 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
526 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
529 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
530 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
531 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
537 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
539 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
541 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
542 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
543 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
546 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
549 pm3393_enable(cmac, enabled);
553 static void pm3393_destroy(struct cmac *cmac)
555 kfree(cmac);
578 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
580 struct cmac *cmac;
582 cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
583 if (!cmac)
586 cmac->ops = &pm3393_ops;
587 cmac->instance = (cmac_instance *) (cmac + 1);
588 cmac->adapter = adapter;
589 cmac->instance->fc = PAUSE_TX | PAUSE_RX;
672 return cmac;