Lines Matching defs:OFFSET
39 #define OFFSET(REG_ADDR) ((REG_ADDR) << 2)
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
420 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
421 t1_tpi_read((mac)->adapter, OFFSET((name)+1), &val1); \
422 t1_tpi_read((mac)->adapter, OFFSET((name)+2), &val2); \
591 t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
592 t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
593 t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
594 t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */
595 t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
596 t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
597 t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
598 t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
599 t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
600 t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
601 t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
602 t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
603 t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
604 t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
605 t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
606 t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
607 t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
608 t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
609 t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
610 t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
611 t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
612 t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */
614 t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */
615 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */
616 t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */
617 t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */
618 t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */
619 t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */
620 t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */
621 t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */
622 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */
623 t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */
624 t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */
625 t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit are undocumented */
626 t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */
628 t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */
629 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */
630 t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */
631 t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */
632 t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */
633 t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */
634 t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */
635 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */
636 t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */
637 t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */
638 t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other bit are undocumented */
640 t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */
641 t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */
642 t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */
643 t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */
644 t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */
645 t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */
647 t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */
648 t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */
650 t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
651 t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */
653 t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */
655 t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
656 t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */
657 t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */
658 t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */
662 t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */
663 t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */
664 t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */
665 t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */
666 t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */
668 t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */
669 t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */
670 t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */
743 t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val);