Lines Matching refs:value
590 u32 value = readl(ioaddr + XGMAC_CONTROL);
591 value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
592 writel(value, ioaddr + XGMAC_CONTROL);
594 value = readl(ioaddr + XGMAC_DMA_CONTROL);
595 value |= DMA_CONTROL_ST | DMA_CONTROL_SR;
596 writel(value, ioaddr + XGMAC_DMA_CONTROL);
601 u32 value = readl(ioaddr + XGMAC_DMA_CONTROL);
602 value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
603 writel(value, ioaddr + XGMAC_DMA_CONTROL);
605 value = readl(ioaddr + XGMAC_CONTROL);
606 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
607 writel(value, ioaddr + XGMAC_CONTROL);
906 u32 reg, value;
919 value = readl(priv->base + XGMAC_DMA_STATUS) & 0x700000;
920 } while (value && (value != 0x600000));
944 u32 value, ctrl;
949 /* Save the ctrl register value */
953 value = DMA_BUS_MODE_SFT_RESET;
954 writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
962 value = (0x10 << DMA_BUS_MODE_PBL_SHIFT) |
965 writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
998 * Return value:
1268 * Return value:
1276 unsigned int value = 0;
1286 value |= XGMAC_FRAME_FILTER_PR;
1292 value |= XGMAC_FRAME_FILTER_HUC | XGMAC_FRAME_FILTER_HPF;
1309 value |= XGMAC_FRAME_FILTER_PM;
1315 value |= XGMAC_FRAME_FILTER_HMC | XGMAC_FRAME_FILTER_HPF;
1339 writel(value, ioaddr + XGMAC_FRAME_FILTER);
1348 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1349 * Return value:
1864 u32 value;
1875 value = readl(priv->base + XGMAC_DMA_CONTROL);
1876 value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
1877 writel(value, priv->base + XGMAC_DMA_CONTROL);