Lines Matching defs:base
366 void __iomem *base;
529 xgmac_dma_flush_tx_fifo(priv->base);
661 writel(flow, priv->base + XGMAC_FLOW_CTRL);
663 reg = readl(priv->base + XGMAC_OMR);
665 writel(reg, priv->base + XGMAC_OMR);
667 writel(0, priv->base + XGMAC_FLOW_CTRL);
669 reg = readl(priv->base + XGMAC_OMR);
671 writel(reg, priv->base + XGMAC_OMR);
773 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
774 writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR);
912 writel(0, priv->base + XGMAC_DMA_INTR_ENA);
916 reg = readl(priv->base + XGMAC_DMA_CONTROL);
917 writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
919 value = readl(priv->base + XGMAC_DMA_STATUS) & 0x700000;
926 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
927 writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
930 priv->base + XGMAC_DMA_STATUS);
938 writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_STATUS);
939 writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);
947 void __iomem *ioaddr = priv->base;
1006 void __iomem *ioaddr = priv->base;
1052 if (readl(priv->base + XGMAC_DMA_INTR_ENA))
1055 writel(0, priv->base + XGMAC_DMA_INTR_ENA);
1060 xgmac_mac_disable(priv->base);
1134 writel(1, priv->base + XGMAC_DMA_TX_POLL);
1241 __raw_writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);
1275 void __iomem *ioaddr = priv->base;
1370 void __iomem *ioaddr = priv->base;
1389 intr_status = __raw_readl(priv->base + XGMAC_DMA_STATUS);
1390 intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA);
1391 __raw_writel(intr_status, priv->base + XGMAC_DMA_STATUS);
1423 __raw_writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA);
1446 void __iomem *base = priv->base;
1450 writel(XGMAC_MMC_CTRL_CNT_FRZ, base + XGMAC_MMC_CTRL);
1452 storage->rx_bytes = readl(base + XGMAC_MMC_RXOCTET_G_LO);
1453 storage->rx_bytes |= (u64)(readl(base + XGMAC_MMC_RXOCTET_G_HI)) << 32;
1455 storage->rx_packets = readl(base + XGMAC_MMC_RXFRAME_GB_LO);
1456 storage->multicast = readl(base + XGMAC_MMC_RXMCFRAME_G);
1457 storage->rx_crc_errors = readl(base + XGMAC_MMC_RXCRCERR);
1458 storage->rx_length_errors = readl(base + XGMAC_MMC_RXLENGTHERR);
1459 storage->rx_missed_errors = readl(base + XGMAC_MMC_RXOVERFLOW);
1461 storage->tx_bytes = readl(base + XGMAC_MMC_TXOCTET_G_LO);
1462 storage->tx_bytes |= (u64)(readl(base + XGMAC_MMC_TXOCTET_G_HI)) << 32;
1464 count = readl(base + XGMAC_MMC_TXFRAME_GB_LO);
1465 storage->tx_errors = count - readl(base + XGMAC_MMC_TXFRAME_G_LO);
1467 storage->tx_fifo_errors = readl(base + XGMAC_MMC_TXUNDERFLOW);
1469 writel(0, base + XGMAC_MMC_CTRL);
1476 void __iomem *ioaddr = priv->base;
1493 void __iomem *ioaddr = priv->base;
1527 cmd->base.autoneg = 0;
1528 cmd->base.duplex = DUPLEX_FULL;
1529 cmd->base.speed = 10000;
1599 *data++ = readl(priv->base +
1725 priv->base = ioremap(res->start, resource_size(res));
1726 if (!priv->base) {
1732 uid = readl(priv->base + XGMAC_VERSION);
1736 writel(1, priv->base + XGMAC_ADDR_HIGH(31));
1737 if (readl(priv->base + XGMAC_ADDR_HIGH(31)) == 1)
1742 writel(0, priv->base + XGMAC_DMA_INTR_ENA);
1778 if (readl(priv->base + XGMAC_DMA_HW_FEATURE) & DMA_HW_FEAT_TXCOESEL)
1789 xgmac_get_mac_addr(priv->base, addr, 0);
1808 iounmap(priv->base);
1829 xgmac_mac_disable(priv->base);
1838 iounmap(priv->base);
1871 writel(0, priv->base + XGMAC_DMA_INTR_ENA);
1875 value = readl(priv->base + XGMAC_DMA_CONTROL);
1877 writel(value, priv->base + XGMAC_DMA_CONTROL);
1879 xgmac_pmt(priv->base, priv->wolopts);
1881 xgmac_mac_disable(priv->base);
1890 void __iomem *ioaddr = priv->base;