Lines Matching refs:tp
92 #define tg3_flag(tp, flag) \
93 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
94 #define tg3_flag_set(tp, flag) \
95 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
96 #define tg3_flag_clear(tp, flag) \
97 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
130 #define TG3_MAX_MTU(tp) \
131 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
137 #define TG3_RX_STD_RING_SIZE(tp) \
138 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 #define TG3_RX_JMB_RING_SIZE(tp) \
142 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
146 /* Do not place this n-ring entries value into the tp struct itself,
156 #define TG3_RX_STD_RING_BYTES(tp) \
157 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
158 #define TG3_RX_JMB_RING_BYTES(tp) \
159 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
160 #define TG3_RX_RCB_RING_BYTES(tp) \
161 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
176 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
177 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
179 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
180 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
195 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
197 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
201 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
203 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
213 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
214 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
470 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472 writel(val, tp->regs + off);
475 static u32 tg3_read32(struct tg3 *tp, u32 off)
477 return readl(tp->regs + off);
480 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482 writel(val, tp->aperegs + off);
485 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487 return readl(tp->aperegs + off);
490 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
494 spin_lock_irqsave(&tp->indirect_lock, flags);
495 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
497 spin_unlock_irqrestore(&tp->indirect_lock, flags);
500 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502 writel(val, tp->regs + off);
503 readl(tp->regs + off);
506 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
511 spin_lock_irqsave(&tp->indirect_lock, flags);
512 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
513 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
514 spin_unlock_irqrestore(&tp->indirect_lock, flags);
518 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
528 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
533 spin_lock_irqsave(&tp->indirect_lock, flags);
534 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
536 spin_unlock_irqrestore(&tp->indirect_lock, flags);
543 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
544 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
548 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
553 spin_lock_irqsave(&tp->indirect_lock, flags);
554 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
555 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
556 spin_unlock_irqrestore(&tp->indirect_lock, flags);
565 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
567 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 tp->write32(tp, off, val);
572 tg3_write32(tp, off, val);
575 tp->read32(tp, off);
584 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586 tp->write32_mbox(tp, off, val);
587 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
588 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
589 !tg3_flag(tp, ICH_WORKAROUND)))
590 tp->read32_mbox(tp, off);
593 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
595 void __iomem *mbox = tp->regs + off;
597 if (tg3_flag(tp, TXD_MBOX_HWBUG))
599 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
600 tg3_flag(tp, FLUSH_POSTED_WRITES))
604 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606 return readl(tp->regs + off + GRCMBOX_BASE);
609 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611 writel(val, tp->regs + off + GRCMBOX_BASE);
614 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
615 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
616 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
617 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
618 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
620 #define tw32(reg, val) tp->write32(tp, reg, val)
621 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
622 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
623 #define tr32(reg) tp->read32(tp, reg)
625 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
629 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
633 spin_lock_irqsave(&tp->indirect_lock, flags);
634 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
635 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
647 spin_unlock_irqrestore(&tp->indirect_lock, flags);
650 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
654 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
660 spin_lock_irqsave(&tp->indirect_lock, flags);
661 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
662 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
663 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
674 spin_unlock_irqrestore(&tp->indirect_lock, flags);
677 static void tg3_ape_lock_init(struct tg3 *tp)
682 if (tg3_asic_rev(tp) == ASIC_REV_5761)
697 if (!tp->pci_fn)
700 bit = 1 << tp->pci_fn;
702 tg3_ape_write32(tp, regbase + 4 * i, bit);
707 static int tg3_ape_lock(struct tg3 *tp, int locknum)
713 if (!tg3_flag(tp, ENABLE_APE))
718 if (tg3_asic_rev(tp) == ASIC_REV_5761)
723 if (!tp->pci_fn)
726 bit = 1 << tp->pci_fn;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
748 tg3_ape_write32(tp, req + off, bit);
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
784 if (!tp->pci_fn)
787 bit = 1 << tp->pci_fn;
799 if (tg3_asic_rev(tp) == ASIC_REV_5761)
804 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
807 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
812 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
815 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
819 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
829 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
834 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
845 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
851 if (!tg3_flag(tp, APE_HAS_NCSI))
854 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
858 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
862 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
865 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
874 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
879 err = tg3_ape_event_lock(tp, 1000);
886 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
888 tg3_ape_write32(tp, bufoff, base_off);
889 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
891 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
892 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
896 if (tg3_ape_wait_for_event(tp, 30000))
900 u32 val = tg3_ape_read32(tp, msgoff + i);
910 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
915 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
919 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
924 err = tg3_ape_event_lock(tp, 20000);
928 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
931 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
932 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
937 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
942 if (!tg3_flag(tp, ENABLE_APE))
947 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
948 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
950 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
952 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
953 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
956 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
958 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
964 if (device_may_wakeup(&tp->pdev->dev) &&
965 tg3_flag(tp, WOL_ENABLE)) {
966 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
972 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
982 tg3_ape_send_event(tp, event);
985 static void tg3_send_ape_heartbeat(struct tg3 *tp,
989 if (!tg3_flag(tp, ENABLE_APE) ||
990 time_before(jiffies, tp->ape_hb_jiffies + interval))
993 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
994 tp->ape_hb_jiffies = jiffies;
997 static void tg3_disable_ints(struct tg3 *tp)
1002 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
1003 for (i = 0; i < tp->irq_max; i++)
1004 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1007 static void tg3_enable_ints(struct tg3 *tp)
1011 tp->irq_sync = 0;
1015 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1017 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1018 for (i = 0; i < tp->irq_cnt; i++) {
1019 struct tg3_napi *tnapi = &tp->napi[i];
1022 if (tg3_flag(tp, 1SHOT_MSI))
1025 tp->coal_now |= tnapi->coal_now;
1029 if (!tg3_flag(tp, TAGGED_STATUS) &&
1030 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1031 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1033 tw32(HOSTCC_MODE, tp->coal_now);
1035 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1040 struct tg3 *tp = tnapi->tp;
1045 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1069 struct tg3 *tp = tnapi->tp;
1077 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1078 tw32(HOSTCC_MODE, tp->coalesce_mode |
1082 static void tg3_switch_clocks(struct tg3 *tp)
1087 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1096 tp->pci_clock_ctrl = clock_ctrl;
1098 if (tg3_flag(tp, 5705_PLUS)) {
1117 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1124 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1126 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1130 tg3_ape_lock(tp, tp->phy_ape_lock);
1161 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1162 tw32_f(MAC_MI_MODE, tp->mi_mode);
1166 tg3_ape_unlock(tp, tp->phy_ape_lock);
1171 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1173 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1176 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1183 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1187 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1189 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1193 tg3_ape_lock(tp, tp->phy_ape_lock);
1220 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1221 tw32_f(MAC_MI_MODE, tp->mi_mode);
1225 tg3_ape_unlock(tp, tp->phy_ape_lock);
1230 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1232 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1235 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1243 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1247 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1258 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1266 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1270 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1275 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1281 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1287 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1292 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1296 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1303 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1307 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1311 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1316 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1321 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1324 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1329 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1339 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1345 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1347 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1351 static int tg3_bmcr_reset(struct tg3 *tp)
1360 err = tg3_writephy(tp, MII_BMCR, phy_control);
1366 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1384 struct tg3 *tp = bp->priv;
1387 spin_lock_bh(&tp->lock);
1389 if (__tg3_readphy(tp, mii_id, reg, &val))
1392 spin_unlock_bh(&tp->lock);
1399 struct tg3 *tp = bp->priv;
1402 spin_lock_bh(&tp->lock);
1404 if (__tg3_writephy(tp, mii_id, reg, val))
1407 spin_unlock_bh(&tp->lock);
1412 static void tg3_mdio_config_5785(struct tg3 *tp)
1417 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1448 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1461 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1462 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1464 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1479 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1480 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1485 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1493 static void tg3_mdio_start(struct tg3 *tp)
1495 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1496 tw32_f(MAC_MI_MODE, tp->mi_mode);
1499 if (tg3_flag(tp, MDIOBUS_INITED) &&
1500 tg3_asic_rev(tp) == ASIC_REV_5785)
1501 tg3_mdio_config_5785(tp);
1504 static int tg3_mdio_init(struct tg3 *tp)
1510 if (tg3_flag(tp, 5717_PLUS)) {
1513 tp->phy_addr = tp->pci_fn + 1;
1515 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1521 tp->phy_addr += 7;
1522 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1525 addr = ssb_gige_get_phyaddr(tp->pdev);
1528 tp->phy_addr = addr;
1530 tp->phy_addr = TG3_PHY_MII_ADDR;
1532 tg3_mdio_start(tp);
1534 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1537 tp->mdio_bus = mdiobus_alloc();
1538 if (tp->mdio_bus == NULL)
1541 tp->mdio_bus->name = "tg3 mdio bus";
1542 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev));
1543 tp->mdio_bus->priv = tp;
1544 tp->mdio_bus->parent = &tp->pdev->dev;
1545 tp->mdio_bus->read = &tg3_mdio_read;
1546 tp->mdio_bus->write = &tg3_mdio_write;
1547 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1554 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1555 tg3_bmcr_reset(tp);
1557 i = mdiobus_register(tp->mdio_bus);
1559 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1560 mdiobus_free(tp->mdio_bus);
1564 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1567 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1568 mdiobus_unregister(tp->mdio_bus);
1569 mdiobus_free(tp->mdio_bus);
1592 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1596 tg3_flag_set(tp, MDIOBUS_INITED);
1598 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1599 tg3_mdio_config_5785(tp);
1604 static void tg3_mdio_fini(struct tg3 *tp)
1606 if (tg3_flag(tp, MDIOBUS_INITED)) {
1607 tg3_flag_clear(tp, MDIOBUS_INITED);
1608 mdiobus_unregister(tp->mdio_bus);
1609 mdiobus_free(tp->mdio_bus);
1613 /* tp->lock is held. */
1614 static inline void tg3_generate_fw_event(struct tg3 *tp)
1622 tp->last_event_jiffies = jiffies;
1627 /* tp->lock is held. */
1628 static void tg3_wait_for_event_ack(struct tg3 *tp)
1635 time_remain = (long)(tp->last_event_jiffies + 1 +
1650 if (pci_channel_offline(tp->pdev))
1657 /* tp->lock is held. */
1658 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1663 if (!tg3_readphy(tp, MII_BMCR, ®))
1665 if (!tg3_readphy(tp, MII_BMSR, ®))
1670 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1672 if (!tg3_readphy(tp, MII_LPA, ®))
1677 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1678 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1680 if (!tg3_readphy(tp, MII_STAT1000, ®))
1685 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1692 /* tp->lock is held. */
1693 static void tg3_ump_link_report(struct tg3 *tp)
1697 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1700 tg3_phy_gather_ump_data(tp, data);
1702 tg3_wait_for_event_ack(tp);
1704 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1711 tg3_generate_fw_event(tp);
1714 /* tp->lock is held. */
1715 static void tg3_stop_fw(struct tg3 *tp)
1717 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1719 tg3_wait_for_event_ack(tp);
1721 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1723 tg3_generate_fw_event(tp);
1726 tg3_wait_for_event_ack(tp);
1730 /* tp->lock is held. */
1731 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1733 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1736 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1739 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1759 /* tp->lock is held. */
1760 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1762 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1765 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1770 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1780 /* tp->lock is held. */
1781 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1783 if (tg3_flag(tp, ENABLE_ASF)) {
1786 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1806 static int tg3_poll_fw(struct tg3 *tp)
1811 if (tg3_flag(tp, NO_FWARE_REPORTED))
1814 if (tg3_flag(tp, IS_SSB_CORE)) {
1819 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1824 if (pci_channel_offline(tp->pdev))
1834 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1837 if (pci_channel_offline(tp->pdev)) {
1838 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1839 tg3_flag_set(tp, NO_FWARE_REPORTED);
1840 netdev_info(tp->dev, "No firmware running\n");
1854 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1855 tg3_flag_set(tp, NO_FWARE_REPORTED);
1857 netdev_info(tp->dev, "No firmware running\n");
1860 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1870 static void tg3_link_report(struct tg3 *tp)
1872 if (!netif_carrier_ok(tp->dev)) {
1873 netif_info(tp, link, tp->dev, "Link is down\n");
1874 tg3_ump_link_report(tp);
1875 } else if (netif_msg_link(tp)) {
1876 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1877 (tp->link_config.active_speed == SPEED_1000 ?
1879 (tp->link_config.active_speed == SPEED_100 ?
1881 (tp->link_config.active_duplex == DUPLEX_FULL ?
1884 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1885 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1887 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1890 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1891 netdev_info(tp->dev, "EEE is %s\n",
1892 tp->setlpicnt ? "enabled" : "disabled");
1894 tg3_ump_link_report(tp);
1897 tp->link_up = netif_carrier_ok(tp->dev);
1960 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1964 u32 old_rx_mode = tp->rx_mode;
1965 u32 old_tx_mode = tp->tx_mode;
1967 if (tg3_flag(tp, USE_PHYLIB))
1968 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1970 autoneg = tp->link_config.autoneg;
1972 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1973 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1978 flowctrl = tp->link_config.flowctrl;
1980 tp->link_config.active_flowctrl = flowctrl;
1983 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1985 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1987 if (old_rx_mode != tp->rx_mode)
1988 tw32_f(MAC_RX_MODE, tp->rx_mode);
1991 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1993 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1995 if (old_tx_mode != tp->tx_mode)
1996 tw32_f(MAC_TX_MODE, tp->tx_mode);
2003 struct tg3 *tp = netdev_priv(dev);
2004 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2006 spin_lock_bh(&tp->lock);
2008 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2011 oldflowctrl = tp->link_config.active_flowctrl;
2020 tg3_asic_rev(tp) != ASIC_REV_5785)
2029 tp->link_config.flowctrl);
2037 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2041 if (mac_mode != tp->mac_mode) {
2042 tp->mac_mode = mac_mode;
2043 tw32_f(MAC_MODE, tp->mac_mode);
2047 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2067 if (phydev->link != tp->old_link ||
2068 phydev->speed != tp->link_config.active_speed ||
2069 phydev->duplex != tp->link_config.active_duplex ||
2070 oldflowctrl != tp->link_config.active_flowctrl)
2073 tp->old_link = phydev->link;
2074 tp->link_config.active_speed = phydev->speed;
2075 tp->link_config.active_duplex = phydev->duplex;
2077 spin_unlock_bh(&tp->lock);
2080 tg3_link_report(tp);
2083 static int tg3_phy_init(struct tg3 *tp)
2087 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2091 tg3_bmcr_reset(tp);
2093 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2096 phydev = phy_connect(tp->dev, phydev_name(phydev),
2099 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2107 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2118 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2122 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2129 static void tg3_phy_start(struct tg3 *tp)
2133 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2136 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2138 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2139 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2140 phydev->speed = tp->link_config.speed;
2141 phydev->duplex = tp->link_config.duplex;
2142 phydev->autoneg = tp->link_config.autoneg;
2144 phydev->advertising, tp->link_config.advertising);
2152 static void tg3_phy_stop(struct tg3 *tp)
2154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2157 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2160 static void tg3_phy_fini(struct tg3 *tp)
2162 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2163 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2164 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2168 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2173 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2176 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2178 err = tg3_phy_auxctl_write(tp,
2185 err = tg3_phy_auxctl_read(tp,
2191 err = tg3_phy_auxctl_write(tp,
2198 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2202 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2205 tg3_writephy(tp, MII_TG3_FET_TEST,
2207 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2212 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2214 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2218 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2222 if (!tg3_flag(tp, 5705_PLUS) ||
2223 (tg3_flag(tp, 5717_PLUS) &&
2224 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2227 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2228 tg3_phy_fet_toggle_apd(tp, enable);
2236 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2239 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2246 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2249 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2253 if (!tg3_flag(tp, 5705_PLUS) ||
2254 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2257 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2260 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2263 tg3_writephy(tp, MII_TG3_FET_TEST,
2265 if (!tg3_readphy(tp, reg, &phy)) {
2270 tg3_writephy(tp, reg, phy);
2272 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2277 ret = tg3_phy_auxctl_read(tp,
2284 tg3_phy_auxctl_write(tp,
2290 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2295 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2298 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2300 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2304 static void tg3_phy_apply_otp(struct tg3 *tp)
2308 if (!tp->phy_otp)
2311 otp = tp->phy_otp;
2313 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2318 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2322 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2329 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2332 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2338 tg3_phy_toggle_auxctl_smdsp(tp, false);
2341 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2344 struct ethtool_eee *dest = &tp->eee;
2346 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2352 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2368 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2381 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2385 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2388 tp->setlpicnt = 0;
2390 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2392 tp->link_config.active_duplex == DUPLEX_FULL &&
2393 (tp->link_config.active_speed == SPEED_100 ||
2394 tp->link_config.active_speed == SPEED_1000)) {
2397 if (tp->link_config.active_speed == SPEED_1000)
2404 tg3_eee_pull_config(tp, NULL);
2405 if (tp->eee.eee_active)
2406 tp->setlpicnt = 2;
2409 if (!tp->setlpicnt) {
2411 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2412 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2413 tg3_phy_toggle_auxctl_smdsp(tp, false);
2421 static void tg3_phy_eee_enable(struct tg3 *tp)
2425 if (tp->link_config.active_speed == SPEED_1000 &&
2426 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2427 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2428 tg3_flag(tp, 57765_CLASS)) &&
2429 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2432 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2433 tg3_phy_toggle_auxctl_smdsp(tp, false);
2440 static int tg3_wait_macro_done(struct tg3 *tp)
2447 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2458 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2471 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2473 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2480 if (tg3_wait_macro_done(tp)) {
2485 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2487 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2488 if (tg3_wait_macro_done(tp)) {
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2494 if (tg3_wait_macro_done(tp)) {
2502 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2503 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2504 tg3_wait_macro_done(tp)) {
2512 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2524 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2531 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2533 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2535 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2536 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2537 if (tg3_wait_macro_done(tp))
2544 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2553 err = tg3_bmcr_reset(tp);
2560 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2564 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2567 tg3_writephy(tp, MII_BMCR,
2571 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2574 tg3_writephy(tp, MII_CTRL1000,
2577 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2582 tg3_phydsp_write(tp, 0x8005, 0x0800);
2584 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2589 err = tg3_phy_reset_chanpat(tp);
2593 tg3_phydsp_write(tp, 0x8005, 0x0000);
2595 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2596 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2598 tg3_phy_toggle_auxctl_smdsp(tp, false);
2600 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2602 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2607 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2612 static void tg3_carrier_off(struct tg3 *tp)
2614 netif_carrier_off(tp->dev);
2615 tp->link_up = false;
2618 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2620 if (tg3_flag(tp, ENABLE_ASF))
2621 netdev_warn(tp->dev,
2628 static int tg3_phy_reset(struct tg3 *tp)
2633 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2638 err = tg3_readphy(tp, MII_BMSR, &val);
2639 err |= tg3_readphy(tp, MII_BMSR, &val);
2643 if (netif_running(tp->dev) && tp->link_up) {
2644 netif_carrier_off(tp->dev);
2645 tg3_link_report(tp);
2648 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2649 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2650 tg3_asic_rev(tp) == ASIC_REV_5705) {
2651 err = tg3_phy_reset_5703_4_5(tp);
2658 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2659 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2666 err = tg3_bmcr_reset(tp);
2672 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2677 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2678 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2688 if (tg3_flag(tp, 5717_PLUS) &&
2689 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2692 tg3_phy_apply_otp(tp);
2694 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2695 tg3_phy_toggle_apd(tp, true);
2697 tg3_phy_toggle_apd(tp, false);
2700 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2701 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2702 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2703 tg3_phydsp_write(tp, 0x000a, 0x0323);
2704 tg3_phy_toggle_auxctl_smdsp(tp, false);
2707 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2709 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2712 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2713 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2714 tg3_phydsp_write(tp, 0x000a, 0x310b);
2715 tg3_phydsp_write(tp, 0x201f, 0x9506);
2716 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2717 tg3_phy_toggle_auxctl_smdsp(tp, false);
2719 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2720 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2722 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2723 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2724 tg3_writephy(tp, MII_TG3_TEST1,
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2729 tg3_phy_toggle_auxctl_smdsp(tp, false);
2735 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2737 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2738 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2740 err = tg3_phy_auxctl_read(tp,
2743 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2750 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2751 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2752 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2756 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2758 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2761 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2762 tg3_phydsp_write(tp, 0xffb, 0x4000);
2764 tg3_phy_toggle_automdix(tp, true);
2765 tg3_phy_set_wirespeed(tp);
2785 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2789 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2790 tg3_asic_rev(tp) == ASIC_REV_5719)
2791 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2795 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2799 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2800 tg3_asic_rev(tp) == ASIC_REV_5719)
2801 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2808 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2810 if (!tg3_flag(tp, IS_NIC))
2813 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2814 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2815 tg3_asic_rev(tp) == ASIC_REV_5720) {
2816 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2819 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2821 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2824 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2826 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2833 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2837 if (!tg3_flag(tp, IS_NIC) ||
2838 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2839 tg3_asic_rev(tp) == ASIC_REV_5701)
2842 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2857 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2859 if (!tg3_flag(tp, IS_NIC))
2862 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2863 tg3_asic_rev(tp) == ASIC_REV_5701) {
2864 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2871 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2872 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2879 tp->grc_local_ctrl;
2895 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2897 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2903 no_gpio2 = tp->nic_sram_data_cfg &
2916 tp->grc_local_ctrl | grc_local_ctrl,
2922 tp->grc_local_ctrl | grc_local_ctrl,
2928 tp->grc_local_ctrl | grc_local_ctrl,
2934 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2939 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2942 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2945 msg = tg3_set_function_status(tp, msg);
2951 tg3_pwrsrc_switch_to_vaux(tp);
2953 tg3_pwrsrc_die_with_vmain(tp);
2956 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2959 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2964 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2967 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2968 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2969 tg3_asic_rev(tp) == ASIC_REV_5720) {
2970 tg3_frob_aux_power_5717(tp, include_wol ?
2971 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2975 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2978 dev_peer = pci_get_drvdata(tp->pdev_peer);
2993 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2994 tg3_flag(tp, ENABLE_ASF))
2998 tg3_pwrsrc_switch_to_vaux(tp);
3000 tg3_pwrsrc_die_with_vmain(tp);
3003 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3005 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3007 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3016 static bool tg3_phy_power_bug(struct tg3 *tp)
3018 switch (tg3_asic_rev(tp)) {
3023 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3027 if (!tp->pci_fn)
3032 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3033 !tp->pci_fn)
3041 static bool tg3_phy_led_bug(struct tg3 *tp)
3043 switch (tg3_asic_rev(tp)) {
3046 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3047 !tp->pci_fn)
3055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3059 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3062 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3063 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3075 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3076 tg3_bmcr_reset(tp);
3081 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3083 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3086 tg3_writephy(tp, MII_ADVERTISE, 0);
3087 tg3_writephy(tp, MII_BMCR,
3090 tg3_writephy(tp, MII_TG3_FET_TEST,
3092 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3094 tg3_writephy(tp,
3098 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3102 if (!tg3_phy_led_bug(tp))
3103 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3109 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3115 if (tg3_phy_power_bug(tp))
3118 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3119 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3126 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3129 /* tp->lock is held. */
3130 static int tg3_nvram_lock(struct tg3 *tp)
3132 if (tg3_flag(tp, NVRAM)) {
3135 if (tp->nvram_lock_cnt == 0) {
3147 tp->nvram_lock_cnt++;
3152 /* tp->lock is held. */
3153 static void tg3_nvram_unlock(struct tg3 *tp)
3155 if (tg3_flag(tp, NVRAM)) {
3156 if (tp->nvram_lock_cnt > 0)
3157 tp->nvram_lock_cnt--;
3158 if (tp->nvram_lock_cnt == 0)
3163 /* tp->lock is held. */
3164 static void tg3_enable_nvram_access(struct tg3 *tp)
3166 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3173 /* tp->lock is held. */
3174 static void tg3_disable_nvram_access(struct tg3 *tp)
3176 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3183 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3225 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3244 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3246 if (tg3_flag(tp, NVRAM) &&
3247 tg3_flag(tp, NVRAM_BUFFERED) &&
3248 tg3_flag(tp, FLASH) &&
3249 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3250 (tp->nvram_jedecnum == JEDEC_ATMEL))
3252 addr = ((addr / tp->nvram_pagesize) <<
3254 (addr % tp->nvram_pagesize);
3259 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3261 if (tg3_flag(tp, NVRAM) &&
3262 tg3_flag(tp, NVRAM_BUFFERED) &&
3263 tg3_flag(tp, FLASH) &&
3264 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3265 (tp->nvram_jedecnum == JEDEC_ATMEL))
3268 tp->nvram_pagesize) +
3280 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3284 if (!tg3_flag(tp, NVRAM))
3285 return tg3_nvram_read_using_eeprom(tp, offset, val);
3287 offset = tg3_nvram_phys_addr(tp, offset);
3292 ret = tg3_nvram_lock(tp);
3296 tg3_enable_nvram_access(tp);
3299 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3305 tg3_disable_nvram_access(tp);
3307 tg3_nvram_unlock(tp);
3313 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3316 int res = tg3_nvram_read(tp, offset, &v);
3322 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3372 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3376 u32 pagesize = tp->nvram_pagesize;
3392 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3411 tg3_enable_nvram_access(tp);
3419 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3428 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3434 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3454 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3463 tg3_nvram_exec_cmd(tp, nvram_cmd);
3471 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3483 page_off = offset % tp->nvram_pagesize;
3485 phy_addr = tg3_nvram_phys_addr(tp, offset);
3491 if (page_off == (tp->nvram_pagesize - 4))
3498 !tg3_flag(tp, FLASH) ||
3499 !tg3_flag(tp, 57765_PLUS))
3502 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3503 !tg3_flag(tp, 5755_PLUS) &&
3504 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 ret = tg3_nvram_exec_cmd(tp, cmd);
3513 if (!tg3_flag(tp, FLASH)) {
3518 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3526 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3530 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3531 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 if (!tg3_flag(tp, NVRAM)) {
3537 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3541 ret = tg3_nvram_lock(tp);
3545 tg3_enable_nvram_access(tp);
3546 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3552 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3553 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3556 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3563 tg3_disable_nvram_access(tp);
3564 tg3_nvram_unlock(tp);
3567 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3568 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3580 /* tp->lock is held. */
3581 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3591 if (pci_channel_offline(tp->pdev))
3598 /* tp->lock is held. */
3599 static int tg3_rxcpu_pause(struct tg3 *tp)
3601 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3610 /* tp->lock is held. */
3611 static int tg3_txcpu_pause(struct tg3 *tp)
3613 return tg3_pause_cpu(tp, TX_CPU_BASE);
3616 /* tp->lock is held. */
3617 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3623 /* tp->lock is held. */
3624 static void tg3_rxcpu_resume(struct tg3 *tp)
3626 tg3_resume_cpu(tp, RX_CPU_BASE);
3629 /* tp->lock is held. */
3630 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3634 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3636 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3643 rc = tg3_rxcpu_pause(tp);
3649 if (tg3_flag(tp, IS_SSB_CORE))
3652 rc = tg3_txcpu_pause(tp);
3656 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3662 if (tg3_flag(tp, NVRAM))
3667 static int tg3_fw_data_len(struct tg3 *tp,
3676 * tp->fw->size minus headers.
3686 if (tp->fw_len == 0xffffffff)
3689 fw_len = tp->fw->size;
3694 /* tp->lock is held. */
3695 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3701 int total_len = tp->fw->size;
3703 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3704 netdev_err(tp->dev,
3710 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3715 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3719 int lock_err = tg3_nvram_lock(tp);
3720 err = tg3_halt_cpu(tp, cpu_base);
3722 tg3_nvram_unlock(tp);
3727 write_op(tp, cpu_scratch_base + i, 0);
3741 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3742 write_op(tp, cpu_scratch_base +
3760 /* tp->lock is held. */
3761 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3781 /* tp->lock is held. */
3782 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3787 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3795 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3801 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3808 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3811 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3818 tg3_rxcpu_resume(tp);
3823 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3840 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3844 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3846 netdev_warn(tp->dev,
3854 /* tp->lock is held. */
3855 static void tg3_load_57766_firmware(struct tg3 *tp)
3859 if (!tg3_flag(tp, NO_NVRAM))
3862 if (tg3_validate_rxcpu_state(tp))
3865 if (!tp->fw)
3882 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3886 if (tg3_rxcpu_pause(tp))
3890 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3892 tg3_rxcpu_resume(tp);
3895 /* tp->lock is held. */
3896 static int tg3_load_tso_firmware(struct tg3 *tp)
3902 if (!tg3_flag(tp, FW_TSO))
3905 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3913 cpu_scratch_size = tp->fw_len;
3915 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3924 err = tg3_load_firmware_cpu(tp, cpu_base,
3931 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3934 netdev_err(tp->dev,
3941 tg3_resume_cpu(tp, cpu_base);
3945 /* tp->lock is held. */
3946 static void __tg3_set_one_mac_addr(struct tg3 *tp, const u8 *mac_addr,
3965 /* tp->lock is held. */
3966 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3974 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3977 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3978 tg3_asic_rev(tp) == ASIC_REV_5704) {
3980 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3983 addr_high = (tp->dev->dev_addr[0] +
3984 tp->dev->dev_addr[1] +
3985 tp->dev->dev_addr[2] +
3986 tp->dev->dev_addr[3] +
3987 tp->dev->dev_addr[4] +
3988 tp->dev->dev_addr[5]) &
3993 static void tg3_enable_register_access(struct tg3 *tp)
3999 pci_write_config_dword(tp->pdev,
4000 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4003 static int tg3_power_up(struct tg3 *tp)
4007 tg3_enable_register_access(tp);
4009 err = pci_set_power_state(tp->pdev, PCI_D0);
4012 tg3_pwrsrc_switch_to_vmain(tp);
4014 netdev_err(tp->dev, "Transition to D0 failed\n");
4022 static int tg3_power_down_prepare(struct tg3 *tp)
4027 tg3_enable_register_access(tp);
4030 if (tg3_flag(tp, CLKREQ_BUG))
4031 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4038 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4039 tg3_flag(tp, WOL_ENABLE);
4041 if (tg3_flag(tp, USE_PHYLIB)) {
4043 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4044 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4049 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
4051 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4053 tp->link_config.speed = phydev->speed;
4054 tp->link_config.duplex = phydev->duplex;
4055 tp->link_config.autoneg = phydev->autoneg;
4057 &tp->link_config.advertising,
4068 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4069 if (tg3_flag(tp, WOL_SPEED_100MB)) {
4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4101 tg3_setup_phy(tp, false);
4104 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4109 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4114 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4120 if (tg3_flag(tp, WOL_CAP))
4121 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4132 tg3_phy_auxctl_write(tp,
4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4142 else if (tp->phy_flags &
4144 if (tp->link_config.active_speed == SPEED_1000)
4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4152 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4153 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4155 if (tg3_5700_link_polarity(tp, speed))
4164 if (!tg3_flag(tp, 5750_PLUS))
4165 tw32(MAC_LED_CTRL, tp->led_ctrl);
4168 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4169 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4172 if (tg3_flag(tp, ENABLE_APE))
4184 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4185 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4186 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4189 base_val = tp->pci_clock_ctrl;
4195 } else if (tg3_flag(tp, 5780_CLASS) ||
4196 tg3_flag(tp, CPMU_PRESENT) ||
4197 tg3_asic_rev(tp) == ASIC_REV_5906) {
4199 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4202 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4203 tg3_asic_rev(tp) == ASIC_REV_5701) {
4208 } else if (tg3_flag(tp, 5705_PLUS)) {
4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4222 if (!tg3_flag(tp, 5705_PLUS)) {
4225 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4226 tg3_asic_rev(tp) == ASIC_REV_5701) {
4235 tp->pci_clock_ctrl | newbits3, 40);
4239 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4240 tg3_power_down_phy(tp, do_low_power);
4242 tg3_frob_aux_power(tp, true);
4245 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4246 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4247 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4252 if (!tg3_flag(tp, ENABLE_ASF)) {
4255 err = tg3_nvram_lock(tp);
4256 tg3_halt_cpu(tp, RX_CPU_BASE);
4258 tg3_nvram_unlock(tp);
4262 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4264 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4269 static void tg3_power_down(struct tg3 *tp)
4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4272 pci_set_power_state(tp->pdev, PCI_D3hot);
4275 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4322 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4338 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4339 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4353 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4365 if (!tp->eee.eee_enabled) {
4367 tp->eee.advertised = 0;
4369 tp->eee.advertised = advertise &
4374 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4378 switch (tg3_asic_rev(tp)) {
4388 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4392 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4393 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4397 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4406 static void tg3_phy_copper_begin(struct tg3 *tp)
4408 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4409 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4412 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4413 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4416 if (tg3_flag(tp, WOL_SPEED_100MB))
4419 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4420 if (!(tp->phy_flags &
4428 adv = tp->link_config.advertising;
4429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4433 fc = tp->link_config.flowctrl;
4436 tg3_phy_autoneg_cfg(tp, adv, fc);
4438 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4439 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4447 tg3_writephy(tp, MII_BMCR,
4453 tp->link_config.active_speed = tp->link_config.speed;
4454 tp->link_config.active_duplex = tp->link_config.duplex;
4456 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4461 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4465 switch (tp->link_config.speed) {
4479 if (tp->link_config.duplex == DUPLEX_FULL)
4482 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4484 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4489 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4490 tg3_readphy(tp, MII_BMSR, &tmp))
4497 tg3_writephy(tp, MII_BMCR, bmcr);
4503 static int tg3_phy_pull_config(struct tg3 *tp)
4508 err = tg3_readphy(tp, MII_BMCR, &val);
4513 tp->link_config.autoneg = AUTONEG_DISABLE;
4514 tp->link_config.advertising = 0;
4515 tg3_flag_clear(tp, PAUSE_AUTONEG);
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4524 tp->link_config.speed = SPEED_10;
4527 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4530 tp->link_config.speed = SPEED_100;
4533 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4534 tp->link_config.speed = SPEED_1000;
4543 tp->link_config.duplex = DUPLEX_FULL;
4545 tp->link_config.duplex = DUPLEX_HALF;
4547 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4553 tp->link_config.autoneg = AUTONEG_ENABLE;
4554 tp->link_config.advertising = ADVERTISED_Autoneg;
4555 tg3_flag_set(tp, PAUSE_AUTONEG);
4557 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4560 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4565 tp->link_config.advertising |= adv | ADVERTISED_TP;
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4569 tp->link_config.advertising |= ADVERTISED_FIBRE;
4572 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4576 err = tg3_readphy(tp, MII_CTRL1000, &val);
4582 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4587 tp->link_config.flowctrl = adv;
4593 tp->link_config.advertising |= adv;
4600 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4606 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4608 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4609 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4610 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4612 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4619 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4623 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4626 tg3_eee_pull_config(tp, &eee);
4628 if (tp->eee.eee_enabled) {
4629 if (tp->eee.advertised != eee.advertised ||
4630 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4631 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4642 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4646 advertising = tp->link_config.advertising;
4650 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4651 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4655 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4661 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4666 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4670 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4671 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4686 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4693 if (tg3_readphy(tp, MII_STAT1000, &val))
4699 if (tg3_readphy(tp, MII_LPA, rmtadv))
4703 tp->link_config.rmt_adv = lpeth;
4708 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4710 if (curr_link_up != tp->link_up) {
4712 netif_carrier_on(tp->dev);
4714 netif_carrier_off(tp->dev);
4715 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4716 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4719 tg3_link_report(tp);
4726 static void tg3_clear_mac_status(struct tg3 *tp)
4738 static void tg3_setup_eee(struct tg3 *tp)
4744 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4753 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4757 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4760 if (tg3_flag(tp, ENABLE_APE))
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4767 (tp->eee.tx_lpi_timer & 0xffff));
4774 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4783 tg3_clear_mac_status(tp);
4785 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4787 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4791 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4796 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4797 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4798 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4799 tp->link_up) {
4800 tg3_readphy(tp, MII_BMSR, &bmsr);
4801 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4806 tg3_phy_reset(tp);
4808 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4809 tg3_readphy(tp, MII_BMSR, &bmsr);
4810 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4811 !tg3_flag(tp, INIT_COMPLETE))
4815 err = tg3_init_5401phy_dsp(tp);
4819 tg3_readphy(tp, MII_BMSR, &bmsr);
4822 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4829 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4832 tp->link_config.active_speed == SPEED_1000) {
4833 err = tg3_phy_reset(tp);
4835 err = tg3_init_5401phy_dsp(tp);
4840 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4841 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4843 tg3_writephy(tp, 0x15, 0x0a75);
4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4850 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4855 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4858 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4859 tg3_asic_rev(tp) == ASIC_REV_5701) {
4860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4870 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4871 tp->link_config.rmt_adv = 0;
4873 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4874 err = tg3_phy_auxctl_read(tp,
4878 tg3_phy_auxctl_write(tp,
4887 tg3_readphy(tp, MII_BMSR, &bmsr);
4888 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4897 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4900 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4905 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4911 tg3_readphy(tp, MII_BMCR, &bmcr);
4912 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4922 tp->link_config.active_speed = current_speed;
4923 tp->link_config.active_duplex = current_duplex;
4925 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4926 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4930 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4931 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4939 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4941 tg3_setup_eee(tp);
4942 tg3_phy_reset(tp);
4946 tp->link_config.speed == current_speed &&
4947 tp->link_config.duplex == current_duplex) {
4953 tp->link_config.active_duplex == DUPLEX_FULL) {
4956 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4964 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4965 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4967 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4972 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4973 tg3_phy_copper_begin(tp);
4975 if (tg3_flag(tp, ROBOSWITCH)) {
4980 tp->link_config.active_speed = current_speed;
4981 tp->link_config.active_duplex = current_duplex;
4984 tg3_readphy(tp, MII_BMSR, &bmsr);
4985 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4986 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4990 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4992 if (tp->link_config.active_speed == SPEED_100 ||
4993 tp->link_config.active_speed == SPEED_10)
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4996 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4997 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5005 if (tg3_flag(tp, RGMII_MODE)) {
5009 if (tp->link_config.active_speed == SPEED_10)
5011 else if (tp->link_config.active_speed == SPEED_100)
5014 else if (tp->link_config.active_speed == SPEED_1000)
5022 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5023 if (tp->link_config.active_duplex == DUPLEX_HALF)
5024 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5026 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5028 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5029 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5031 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5037 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5038 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5039 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5040 tw32_f(MAC_MI_MODE, tp->mi_mode);
5044 tw32_f(MAC_MODE, tp->mac_mode);
5047 tg3_phy_eee_adjust(tp, current_link_up);
5049 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5057 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5059 tp->link_config.active_speed == SPEED_1000 &&
5060 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5066 tg3_write_mem(tp,
5072 if (tg3_flag(tp, CLKREQ_BUG)) {
5073 if (tp->link_config.active_speed == SPEED_100 ||
5074 tp->link_config.active_speed == SPEED_10)
5075 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5078 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5082 tg3_test_and_report_link_chg(tp, current_link_up);
5151 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5231 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5232 tw32_f(MAC_MODE, tp->mac_mode);
5254 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5260 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5261 tw32_f(MAC_MODE, tp->mac_mode);
5275 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5276 tw32_f(MAC_MODE, tp->mac_mode);
5361 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5362 tw32_f(MAC_MODE, tp->mac_mode);
5403 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5413 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5426 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5433 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5434 tw32_f(MAC_MODE, tp->mac_mode);
5448 static void tg3_init_bcm8002(struct tg3 *tp)
5454 if (tg3_flag(tp, INIT_COMPLETE) &&
5459 tg3_writephy(tp, 0x16, 0x8007);
5462 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5470 tg3_writephy(tp, 0x10, 0x8411);
5473 tg3_writephy(tp, 0x11, 0x0a10);
5475 tg3_writephy(tp, 0x18, 0x00a0);
5476 tg3_writephy(tp, 0x16, 0x41ff);
5479 tg3_writephy(tp, 0x13, 0x0400);
5481 tg3_writephy(tp, 0x13, 0x0000);
5483 tg3_writephy(tp, 0x11, 0x0a50);
5485 tg3_writephy(tp, 0x11, 0x0a10);
5495 tg3_writephy(tp, 0x10, 0x8011);
5498 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5511 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5512 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5524 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5539 tg3_setup_flow_control(tp, 0, 0);
5548 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5555 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5556 tp->serdes_counter &&
5560 tp->serdes_counter--;
5571 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5572 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5592 tp->link_config.rmt_adv =
5595 tg3_setup_flow_control(tp, local_adv, remote_adv);
5597 tp->serdes_counter = 0;
5598 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5600 if (tp->serdes_counter)
5601 tp->serdes_counter--;
5623 tg3_setup_flow_control(tp, 0, 0);
5625 tp->phy_flags |=
5627 tp->serdes_counter =
5634 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5635 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5642 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5649 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5653 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5666 tp->link_config.rmt_adv =
5669 tg3_setup_flow_control(tp, local_adv, remote_adv);
5691 tg3_setup_flow_control(tp, 0, 0);
5696 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5699 tw32_f(MAC_MODE, tp->mac_mode);
5707 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5716 orig_pause_cfg = tp->link_config.active_flowctrl;
5717 orig_active_speed = tp->link_config.active_speed;
5718 orig_active_duplex = tp->link_config.active_duplex;
5720 if (!tg3_flag(tp, HW_AUTONEG) &&
5721 tp->link_up &&
5722 tg3_flag(tp, INIT_COMPLETE)) {
5738 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5739 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5740 tw32_f(MAC_MODE, tp->mac_mode);
5743 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5744 tg3_init_bcm8002(tp);
5750 tp->link_config.rmt_adv = 0;
5753 if (tg3_flag(tp, HW_AUTONEG))
5754 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5756 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5758 tp->napi[0].hw_status->status =
5760 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5775 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5776 tp->serdes_counter == 0) {
5777 tw32_f(MAC_MODE, (tp->mac_mode |
5780 tw32_f(MAC_MODE, tp->mac_mode);
5785 tp->link_config.active_speed = SPEED_1000;
5786 tp->link_config.active_duplex = DUPLEX_FULL;
5787 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5791 tp->link_config.active_speed = SPEED_UNKNOWN;
5792 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5793 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5798 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5799 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5801 orig_active_speed != tp->link_config.active_speed ||
5802 orig_active_duplex != tp->link_config.active_duplex)
5803 tg3_link_report(tp);
5809 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5818 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5819 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5820 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5824 tg3_phy_reset(tp);
5826 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5829 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5834 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5837 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5840 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5849 tw32_f(MAC_MODE, tp->mac_mode);
5852 tg3_clear_mac_status(tp);
5857 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5858 tw32_f(MAC_MODE, tp->mac_mode);
5861 tg3_clear_mac_status(tp);
5864 tg3_phy_reset(tp);
5866 tp->link_config.rmt_adv = 0;
5868 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5869 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5870 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5877 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5879 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5880 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5882 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5885 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5891 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5892 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5895 tg3_writephy(tp, MII_ADVERTISE, newadv);
5897 tg3_writephy(tp, MII_BMCR, bmcr);
5900 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5901 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5911 if (tp->link_config.duplex == DUPLEX_FULL)
5921 if (tp->link_up) {
5924 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5928 tg3_writephy(tp, MII_ADVERTISE, adv);
5929 tg3_writephy(tp, MII_BMCR, bmcr |
5933 tg3_carrier_off(tp);
5935 tg3_writephy(tp, MII_BMCR, new_bmcr);
5937 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5938 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5939 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5945 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5963 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5964 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5973 tp->link_config.rmt_adv =
5975 } else if (!tg3_flag(tp, 5780_CLASS)) {
5985 tg3_setup_flow_control(tp, local_adv, remote_adv);
5987 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5988 if (tp->link_config.active_duplex == DUPLEX_HALF)
5989 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5991 tw32_f(MAC_MODE, tp->mac_mode);
5996 tp->link_config.active_speed = current_speed;
5997 tp->link_config.active_duplex = current_duplex;
5999 tg3_test_and_report_link_chg(tp, current_link_up);
6003 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6005 if (tp->serdes_counter) {
6007 tp->serdes_counter--;
6011 if (!tp->link_up &&
6012 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6015 tg3_readphy(tp, MII_BMCR, &bmcr);
6020 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6021 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6024 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6026 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6027 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6037 tg3_writephy(tp, MII_BMCR, bmcr);
6038 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6041 } else if (tp->link_up &&
6042 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6043 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6047 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6049 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6054 tg3_readphy(tp, MII_BMCR, &bmcr);
6055 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6057 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6063 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6068 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6069 err = tg3_setup_fiber_phy(tp, force_reset);
6070 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6071 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6073 err = tg3_setup_copper_phy(tp, force_reset);
6075 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6093 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6094 tg3_asic_rev(tp) == ASIC_REV_5762)
6099 if (tp->link_config.active_speed == SPEED_1000 &&
6100 tp->link_config.active_duplex == DUPLEX_HALF)
6107 if (!tg3_flag(tp, 5705_PLUS)) {
6108 if (tp->link_up) {
6110 tp->coal.stats_block_coalesce_usecs);
6116 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6118 if (!tp->link_up)
6120 tp->pwrmgmt_thresh;
6129 /* tp->lock must be held */
6130 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts)
6142 /* tp->lock must be held */
6143 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6153 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6154 static inline void tg3_full_unlock(struct tg3 *tp);
6157 struct tg3 *tp = netdev_priv(dev);
6163 if (tg3_flag(tp, PTP_CAPABLE)) {
6169 if (tp->ptp_clock)
6170 info->phc_index = ptp_clock_index(tp->ptp_clock);
6185 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6196 tg3_full_lock(tp, 0);
6206 tg3_full_unlock(tp);
6213 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6215 tg3_full_lock(tp, 0);
6216 tp->ptp_adjust += delta;
6217 tg3_full_unlock(tp);
6226 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6228 tg3_full_lock(tp, 0);
6229 ns = tg3_refclk_read(tp, sts);
6230 ns += tp->ptp_adjust;
6231 tg3_full_unlock(tp);
6242 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6246 tg3_full_lock(tp, 0);
6247 tg3_refclk_write(tp, ns);
6248 tp->ptp_adjust = 0;
6249 tg3_full_unlock(tp);
6257 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6270 tg3_full_lock(tp, 0);
6281 netdev_warn(tp->dev,
6288 netdev_warn(tp->dev,
6307 tg3_full_unlock(tp);
6333 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6338 tp->ptp_adjust);
6341 /* tp->lock must be held */
6342 static void tg3_ptp_init(struct tg3 *tp)
6344 if (!tg3_flag(tp, PTP_CAPABLE))
6348 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6349 tp->ptp_adjust = 0;
6350 tp->ptp_info = tg3_ptp_caps;
6353 /* tp->lock must be held */
6354 static void tg3_ptp_resume(struct tg3 *tp)
6356 if (!tg3_flag(tp, PTP_CAPABLE))
6359 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6360 tp->ptp_adjust = 0;
6363 static void tg3_ptp_fini(struct tg3 *tp)
6365 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6368 ptp_clock_unregister(tp->ptp_clock);
6369 tp->ptp_clock = NULL;
6370 tp->ptp_adjust = 0;
6373 static inline int tg3_irq_sync(struct tg3 *tp)
6375 return tp->irq_sync;
6378 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6387 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6389 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6390 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6391 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6392 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6393 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6394 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6395 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6396 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6397 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6398 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6399 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6400 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6401 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6402 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6403 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6404 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6405 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6406 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6407 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6409 if (tg3_flag(tp, SUPPORT_MSIX))
6410 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6412 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6413 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6414 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6415 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6416 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6417 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6418 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6419 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6421 if (!tg3_flag(tp, 5705_PLUS)) {
6422 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6423 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6424 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6427 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6428 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6429 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6430 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6431 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6433 if (tg3_flag(tp, NVRAM))
6434 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6437 static void tg3_dump_state(struct tg3 *tp)
6445 if (tp->pdev->error_state != pci_channel_io_normal) {
6446 netdev_err(tp->dev, "PCI channel ERROR!\n");
6454 if (tg3_flag(tp, PCI_EXPRESS)) {
6459 tg3_dump_legacy_regs(tp, regs);
6466 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6473 for (i = 0; i < tp->irq_cnt; i++) {
6474 struct tg3_napi *tnapi = &tp->napi[i];
6477 netdev_err(tp->dev,
6488 netdev_err(tp->dev,
6507 static void tg3_tx_recover(struct tg3 *tp)
6509 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6510 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6512 netdev_warn(tp->dev,
6518 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6535 struct tg3 *tp = tnapi->tp;
6539 int index = tnapi - tp->napi;
6542 if (tg3_flag(tp, ENABLE_TSS))
6545 txq = netdev_get_tx_queue(tp->dev, index);
6553 tg3_tx_recover(tp);
6562 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6567 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping),
6585 dma_unmap_page(&tp->pdev->dev,
6605 tg3_tx_recover(tp);
6639 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6641 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6647 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz,
6665 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6677 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6680 data_size = tp->rx_pkt_map_sz;
6684 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6700 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6712 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp),
6714 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) {
6737 struct tg3 *tp = tnapi->tp;
6740 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6745 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6753 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6804 struct tg3 *tp = tnapi->tp;
6835 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6841 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6860 prefetch(data + TG3_RX_OFFSET(tp));
6872 if (len > TG3_RX_COPY_THRESH(tp)) {
6876 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6881 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size,
6899 skb_reserve(skb, TG3_RX_OFFSET(tp));
6904 skb = netdev_alloc_skb(tp->dev,
6910 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len,
6913 data + TG3_RX_OFFSET(tp),
6915 dma_sync_single_for_device(&tp->pdev->dev, dma_addr,
6921 tg3_hwclock_to_timestamp(tp, tstamp,
6924 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6932 skb->protocol = eth_type_trans(skb, tp->dev);
6934 if (len > (tp->dev->mtu + ETH_HLEN) &&
6942 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6954 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6956 tp->rx_std_ring_mask;
6964 sw_idx &= tp->rx_ret_ring_mask;
6978 if (!tg3_flag(tp, ENABLE_RSS)) {
6984 tp->rx_std_ring_mask;
6990 tp->rx_jmb_ring_mask;
7000 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
7001 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
7003 if (tnapi != &tp->napi[1]) {
7004 tp->rx_refill = true;
7005 napi_schedule(&tp->napi[1].napi);
7012 static void tg3_poll_link(struct tg3 *tp)
7015 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7016 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7021 spin_lock(&tp->lock);
7022 if (tg3_flag(tp, USE_PHYLIB)) {
7030 tg3_setup_phy(tp, false);
7031 spin_unlock(&tp->lock);
7036 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7057 cpycnt = tp->rx_std_ring_mask + 1 -
7061 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7096 tp->rx_std_ring_mask;
7098 tp->rx_std_ring_mask;
7115 cpycnt = tp->rx_jmb_ring_mask + 1 -
7119 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7154 tp->rx_jmb_ring_mask;
7156 tp->rx_jmb_ring_mask;
7164 struct tg3 *tp = tnapi->tp;
7169 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7183 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7184 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7189 tp->rx_refill = false;
7190 for (i = 1; i <= tp->rxq_cnt; i++)
7191 err |= tg3_rx_prodring_xfer(tp, dpr,
7192 &tp->napi[i].prodring);
7205 tw32_f(HOSTCC_MODE, tp->coal_now);
7211 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7213 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7214 schedule_work(&tp->reset_task);
7217 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7219 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7220 cancel_work_sync(&tp->reset_task);
7221 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7227 struct tg3 *tp = tnapi->tp;
7234 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7240 /* tp->last_tag is used in tg3_int_reenable() below
7255 if (tnapi == &tp->napi[1] && tp->rx_refill)
7265 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7266 tw32(HOSTCC_MODE, tp->coalesce_mode |
7274 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7280 tg3_reset_task_schedule(tp);
7284 static void tg3_process_error(struct tg3 *tp)
7289 if (tg3_flag(tp, ERROR_PROCESSED))
7295 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7300 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7305 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7312 tg3_dump_state(tp);
7314 tg3_flag_set(tp, ERROR_PROCESSED);
7315 tg3_reset_task_schedule(tp);
7321 struct tg3 *tp = tnapi->tp;
7327 tg3_process_error(tp);
7329 tg3_poll_link(tp);
7333 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7339 if (tg3_flag(tp, TAGGED_STATUS)) {
7340 /* tp->last_tag is used in tg3_int_reenable() below
7357 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7363 tg3_reset_task_schedule(tp);
7367 static void tg3_napi_disable(struct tg3 *tp)
7371 for (i = tp->irq_cnt - 1; i >= 0; i--)
7372 napi_disable(&tp->napi[i].napi);
7375 static void tg3_napi_enable(struct tg3 *tp)
7379 for (i = 0; i < tp->irq_cnt; i++)
7380 napi_enable(&tp->napi[i].napi);
7383 static void tg3_napi_init(struct tg3 *tp)
7387 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll);
7388 for (i = 1; i < tp->irq_cnt; i++)
7389 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix);
7392 static void tg3_napi_fini(struct tg3 *tp)
7396 for (i = 0; i < tp->irq_cnt; i++)
7397 netif_napi_del(&tp->napi[i].napi);
7400 static inline void tg3_netif_stop(struct tg3 *tp)
7402 netif_trans_update(tp->dev); /* prevent tx timeout */
7403 tg3_napi_disable(tp);
7404 netif_carrier_off(tp->dev);
7405 netif_tx_disable(tp->dev);
7408 /* tp->lock must be held */
7409 static inline void tg3_netif_start(struct tg3 *tp)
7411 tg3_ptp_resume(tp);
7417 netif_tx_wake_all_queues(tp->dev);
7419 if (tp->link_up)
7420 netif_carrier_on(tp->dev);
7422 tg3_napi_enable(tp);
7423 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7424 tg3_enable_ints(tp);
7427 static void tg3_irq_quiesce(struct tg3 *tp)
7428 __releases(tp->lock)
7429 __acquires(tp->lock)
7433 BUG_ON(tp->irq_sync);
7435 tp->irq_sync = 1;
7438 spin_unlock_bh(&tp->lock);
7440 for (i = 0; i < tp->irq_cnt; i++)
7441 synchronize_irq(tp->napi[i].irq_vec);
7443 spin_lock_bh(&tp->lock);
7451 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7453 spin_lock_bh(&tp->lock);
7455 tg3_irq_quiesce(tp);
7458 static inline void tg3_full_unlock(struct tg3 *tp)
7460 spin_unlock_bh(&tp->lock);
7469 struct tg3 *tp = tnapi->tp;
7475 if (likely(!tg3_irq_sync(tp)))
7488 struct tg3 *tp = tnapi->tp;
7501 if (likely(!tg3_irq_sync(tp)))
7510 struct tg3 *tp = tnapi->tp;
7520 if (tg3_flag(tp, CHIP_RESETTING) ||
7539 if (tg3_irq_sync(tp))
7559 struct tg3 *tp = tnapi->tp;
7569 if (tg3_flag(tp, CHIP_RESETTING) ||
7597 if (tg3_irq_sync(tp))
7612 struct tg3 *tp = tnapi->tp;
7617 tg3_disable_ints(tp);
7627 struct tg3 *tp = netdev_priv(dev);
7629 if (tg3_irq_sync(tp))
7632 for (i = 0; i < tp->irq_cnt; i++)
7633 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7639 struct tg3 *tp = netdev_priv(dev);
7641 if (netif_msg_tx_err(tp)) {
7643 tg3_dump_state(tp);
7646 tg3_reset_task_schedule(tp);
7660 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7663 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7672 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7676 if (tg3_flag(tp, 40BIT_DMA_BUG))
7698 struct tg3 *tp = tnapi->tp;
7701 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7707 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7710 if (tg3_40bit_overflow_test(tp, map, len))
7713 if (tp->dma_limit) {
7716 while (len > tp->dma_limit && *budget) {
7717 u32 frag_len = tp->dma_limit;
7718 len -= tp->dma_limit;
7722 len += tp->dma_limit / 2;
7723 frag_len = tp->dma_limit / 2;
7766 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping),
7781 dma_unmap_page(&tnapi->tp->pdev->dev,
7799 struct tg3 *tp = tnapi->tp;
7804 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7818 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data,
7821 if (dma_mapping_error(&tp->pdev->dev, new_addr)) {
7861 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7883 segs = skb_gso_segment(skb, tp->dev->features &
7892 tg3_start_xmit(seg, tp->dev);
7904 struct tg3 *tp = netdev_priv(dev);
7918 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7919 if (tg3_flag(tp, ENABLE_TSS))
7925 * and TX reclaim runs via tp->napi.poll inside of a software
7961 return tg3_tso_bug(tp, tnapi, txq, skb);
7967 tg3_flag(tp, TSO_BUG)) {
7969 return tg3_tso_bug(tp, tnapi, txq, skb);
7984 if (tg3_flag(tp, HW_TSO_1) ||
7985 tg3_flag(tp, HW_TSO_2) ||
7986 tg3_flag(tp, HW_TSO_3)) {
7994 if (tg3_flag(tp, HW_TSO_3)) {
7999 } else if (tg3_flag(tp, HW_TSO_2))
8001 else if (tg3_flag(tp, HW_TSO_1) ||
8002 tg3_asic_rev(tp) == ASIC_REV_5705) {
8030 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8040 tg3_flag(tp, TX_TSTAMP_EN)) {
8047 mapping = dma_map_single(&tp->pdev->dev, skb->data, len,
8049 if (dma_mapping_error(&tp->pdev->dev, mapping))
8058 if (tg3_flag(tp, 5701_DMA_BUG))
8068 if (!tg3_flag(tp, HW_TSO_1) &&
8069 !tg3_flag(tp, HW_TSO_2) &&
8070 !tg3_flag(tp, HW_TSO_3))
8081 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8087 if (dma_mapping_error(&tp->pdev->dev, mapping))
8113 return tg3_tso_bug(tp, tnapi, txq, skb);
8163 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8166 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8169 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8171 if (!tg3_flag(tp, 5705_PLUS))
8172 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8174 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8175 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8177 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8179 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8181 if (tg3_flag(tp, 5705_PLUS) ||
8182 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8183 tg3_asic_rev(tp) == ASIC_REV_5700)
8184 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8187 tw32(MAC_MODE, tp->mac_mode);
8191 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8195 tg3_phy_toggle_apd(tp, false);
8196 tg3_phy_toggle_automdix(tp, false);
8198 if (extlpbk && tg3_phy_set_extloopbk(tp))
8210 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8220 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8221 tg3_readphy(tp, MII_CTRL1000, &val);
8224 tg3_writephy(tp, MII_CTRL1000, val);
8228 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8233 tg3_writephy(tp, MII_BMCR, bmcr);
8236 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8237 tg3_readphy(tp, MII_BMCR, &bmcr);
8241 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8242 tg3_asic_rev(tp) == ASIC_REV_5785) {
8243 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8248 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8252 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8253 tg3_flag(tp, 5780_CLASS)) {
8256 tw32_f(MAC_RX_MODE, tp->rx_mode);
8259 mac_mode = tp->mac_mode &
8266 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8267 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8274 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8286 struct tg3 *tp = netdev_priv(dev);
8289 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8292 spin_lock_bh(&tp->lock);
8293 tg3_mac_loopback(tp, true);
8294 netif_carrier_on(tp->dev);
8295 spin_unlock_bh(&tp->lock);
8298 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8301 spin_lock_bh(&tp->lock);
8302 tg3_mac_loopback(tp, false);
8304 tg3_setup_phy(tp, true);
8305 spin_unlock_bh(&tp->lock);
8313 struct tg3 *tp = netdev_priv(dev);
8315 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8331 static void tg3_rx_prodring_free(struct tg3 *tp,
8336 if (tpr != &tp->napi[0].prodring) {
8338 i = (i + 1) & tp->rx_std_ring_mask)
8339 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8340 tp->rx_pkt_map_sz);
8342 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8345 i = (i + 1) & tp->rx_jmb_ring_mask) {
8346 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8354 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8355 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8356 tp->rx_pkt_map_sz);
8358 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8359 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8360 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8369 * end up in the driver. tp->{tx,}lock are held and thus
8372 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8382 if (tpr != &tp->napi[0].prodring) {
8384 TG3_RX_STD_BUFF_RING_SIZE(tp));
8387 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8392 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8395 if (tg3_flag(tp, 5780_CLASS) &&
8396 tp->dev->mtu > ETH_DATA_LEN)
8398 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8404 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8415 for (i = 0; i < tp->rx_pending; i++) {
8418 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8420 netdev_warn(tp->dev,
8423 "successfully\n", i, tp->rx_pending);
8426 tp->rx_pending = i;
8431 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8434 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8436 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8439 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8450 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8453 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8455 netdev_warn(tp->dev,
8458 "successfully\n", i, tp->rx_jumbo_pending);
8461 tp->rx_jumbo_pending = i;
8470 tg3_rx_prodring_free(tp, tpr);
8474 static void tg3_rx_prodring_fini(struct tg3 *tp,
8482 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8487 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8493 static int tg3_rx_prodring_init(struct tg3 *tp,
8496 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8501 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8502 TG3_RX_STD_RING_BYTES(tp),
8508 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8509 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8514 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8515 TG3_RX_JMB_RING_BYTES(tp),
8525 tg3_rx_prodring_fini(tp, tpr);
8533 * end up in the driver. tp->{tx,}lock is not held and we are not
8536 static void tg3_free_rings(struct tg3 *tp)
8540 for (j = 0; j < tp->irq_cnt; j++) {
8541 struct tg3_napi *tnapi = &tp->napi[j];
8543 tg3_rx_prodring_free(tp, &tnapi->prodring);
8559 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8567 * end up in the driver. tp->{tx,}lock are held and thus
8570 static int tg3_init_rings(struct tg3 *tp)
8575 tg3_free_rings(tp);
8577 for (i = 0; i < tp->irq_cnt; i++) {
8578 struct tg3_napi *tnapi = &tp->napi[i];
8593 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8596 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8597 tg3_free_rings(tp);
8605 static void tg3_mem_tx_release(struct tg3 *tp)
8609 for (i = 0; i < tp->irq_max; i++) {
8610 struct tg3_napi *tnapi = &tp->napi[i];
8613 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8623 static int tg3_mem_tx_acquire(struct tg3 *tp)
8626 struct tg3_napi *tnapi = &tp->napi[0];
8631 if (tg3_flag(tp, ENABLE_TSS))
8634 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8641 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8652 tg3_mem_tx_release(tp);
8656 static void tg3_mem_rx_release(struct tg3 *tp)
8660 for (i = 0; i < tp->irq_max; i++) {
8661 struct tg3_napi *tnapi = &tp->napi[i];
8663 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8668 dma_free_coherent(&tp->pdev->dev,
8669 TG3_RX_RCB_RING_BYTES(tp),
8676 static int tg3_mem_rx_acquire(struct tg3 *tp)
8680 limit = tp->rxq_cnt;
8685 if (tg3_flag(tp, ENABLE_RSS))
8689 struct tg3_napi *tnapi = &tp->napi[i];
8691 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8698 if (!i && tg3_flag(tp, ENABLE_RSS))
8701 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
8702 TG3_RX_RCB_RING_BYTES(tp),
8712 tg3_mem_rx_release(tp);
8720 static void tg3_free_consistent(struct tg3 *tp)
8724 for (i = 0; i < tp->irq_cnt; i++) {
8725 struct tg3_napi *tnapi = &tp->napi[i];
8728 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8735 tg3_mem_rx_release(tp);
8736 tg3_mem_tx_release(tp);
8738 /* tp->hw_stats can be referenced safely:
8740 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set.
8742 if (tp->hw_stats) {
8743 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8744 tp->hw_stats, tp->stats_mapping);
8745 tp->hw_stats = NULL;
8753 static int tg3_alloc_consistent(struct tg3 *tp)
8757 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
8759 &tp->stats_mapping, GFP_KERNEL);
8760 if (!tp->hw_stats)
8763 for (i = 0; i < tp->irq_cnt; i++) {
8764 struct tg3_napi *tnapi = &tp->napi[i];
8767 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
8776 if (tg3_flag(tp, ENABLE_RSS)) {
8805 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8811 tg3_free_consistent(tp);
8818 * clears. tp->lock is held.
8820 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8825 if (tg3_flag(tp, 5705_PLUS)) {
8847 if (pci_channel_offline(tp->pdev)) {
8848 dev_err(&tp->pdev->dev,
8862 dev_err(&tp->pdev->dev,
8871 /* tp->lock is held. */
8872 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8876 tg3_disable_ints(tp);
8878 if (pci_channel_offline(tp->pdev)) {
8879 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8880 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8885 tp->rx_mode &= ~RX_MODE_ENABLE;
8886 tw32_f(MAC_RX_MODE, tp->rx_mode);
8889 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8890 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8891 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8892 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8893 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8894 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8896 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8897 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8898 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8899 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8900 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8901 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8902 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8904 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8905 tw32_f(MAC_MODE, tp->mac_mode);
8908 tp->tx_mode &= ~TX_MODE_ENABLE;
8909 tw32_f(MAC_TX_MODE, tp->tx_mode);
8917 dev_err(&tp->pdev->dev,
8923 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8924 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8925 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8930 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8931 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8934 for (i = 0; i < tp->irq_cnt; i++) {
8935 struct tg3_napi *tnapi = &tp->napi[i];
8944 static void tg3_save_pci_state(struct tg3 *tp)
8946 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8950 static void tg3_restore_pci_state(struct tg3 *tp)
8955 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8956 tp->misc_host_ctrl);
8960 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8961 tg3_flag(tp, PCIX_MODE))
8964 if (tg3_flag(tp, ENABLE_APE))
8968 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8970 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8972 if (!tg3_flag(tp, PCI_EXPRESS)) {
8973 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8974 tp->pci_cacheline_sz);
8975 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8976 tp->pci_lat_timer);
8980 if (tg3_flag(tp, PCIX_MODE)) {
8983 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8986 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8990 if (tg3_flag(tp, 5780_CLASS)) {
8995 if (tg3_flag(tp, USING_MSI)) {
8998 pci_read_config_word(tp->pdev,
8999 tp->msi_cap + PCI_MSI_FLAGS,
9001 pci_write_config_word(tp->pdev,
9002 tp->msi_cap + PCI_MSI_FLAGS,
9010 static void tg3_override_clk(struct tg3 *tp)
9014 switch (tg3_asic_rev(tp)) {
9031 static void tg3_restore_clk(struct tg3 *tp)
9035 switch (tg3_asic_rev(tp)) {
9053 /* tp->lock is held. */
9054 static int tg3_chip_reset(struct tg3 *tp)
9055 __releases(tp->lock)
9056 __acquires(tp->lock)
9062 if (!pci_device_is_present(tp->pdev))
9065 tg3_nvram_lock(tp);
9067 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9072 tp->nvram_lock_cnt = 0;
9078 tg3_save_pci_state(tp);
9080 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9081 tg3_flag(tp, 5755_PLUS))
9090 write_op = tp->write32;
9092 tp->write32 = tg3_write32;
9100 tg3_flag_set(tp, CHIP_RESETTING);
9101 for (i = 0; i < tp->irq_cnt; i++) {
9102 struct tg3_napi *tnapi = &tp->napi[i];
9112 tg3_full_unlock(tp);
9114 for (i = 0; i < tp->irq_cnt; i++)
9115 synchronize_irq(tp->napi[i].irq_vec);
9117 tg3_full_lock(tp, 0);
9119 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9127 if (tg3_flag(tp, PCI_EXPRESS)) {
9129 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9130 !tg3_flag(tp, 57765_PLUS) &&
9135 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9141 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9152 tg3_override_clk(tp);
9155 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9161 tp->write32 = write_op;
9184 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9188 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9191 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9199 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9200 pci_write_config_dword(tp->pdev, 0xc4,
9210 if (!tg3_flag(tp, CPMU_PRESENT))
9212 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9215 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9222 tg3_restore_pci_state(tp);
9224 tg3_flag_clear(tp, CHIP_RESETTING);
9225 tg3_flag_clear(tp, ERROR_PROCESSED);
9228 if (tg3_flag(tp, 5780_CLASS))
9232 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9233 tg3_stop_fw(tp);
9237 if (tg3_flag(tp, IS_SSB_CORE)) {
9243 tg3_stop_fw(tp);
9244 tg3_halt_cpu(tp, RX_CPU_BASE);
9247 err = tg3_poll_fw(tp);
9251 tw32(GRC_MODE, tp->grc_mode);
9253 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9259 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9260 tg3_asic_rev(tp) == ASIC_REV_5705) {
9261 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9262 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9263 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9264 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9267 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9268 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9269 val = tp->mac_mode;
9270 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9271 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9272 val = tp->mac_mode;
9279 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9281 tg3_mdio_start(tp);
9283 if (tg3_flag(tp, PCI_EXPRESS) &&
9284 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9285 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9286 !tg3_flag(tp, 57765_PLUS)) {
9292 tg3_restore_clk(tp);
9297 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
9304 tg3_flag_clear(tp, ENABLE_ASF);
9305 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9308 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9309 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9313 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9315 tg3_flag_set(tp, ENABLE_ASF);
9316 tp->last_event_jiffies = jiffies;
9317 if (tg3_flag(tp, 5750_PLUS))
9318 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9320 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9322 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9324 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9335 /* tp->lock is held. */
9336 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9340 tg3_stop_fw(tp);
9342 tg3_write_sig_pre_reset(tp, kind);
9344 tg3_abort_hw(tp, silent);
9345 err = tg3_chip_reset(tp);
9347 __tg3_set_mac_addr(tp, false);
9349 tg3_write_sig_legacy(tp, kind);
9350 tg3_write_sig_post_reset(tp, kind);
9352 if (tp->hw_stats) {
9354 tg3_get_nstats(tp, &tp->net_stats_prev);
9355 tg3_get_estats(tp, &tp->estats_prev);
9358 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9361 struct tg3_napi *tnapi = &tp->napi[i];
9373 struct tg3 *tp = netdev_priv(dev);
9386 if (tg3_flag(tp, ENABLE_ASF)) {
9399 spin_lock_bh(&tp->lock);
9400 __tg3_set_mac_addr(tp, skip_mac_1);
9402 spin_unlock_bh(&tp->lock);
9407 /* tp->lock is held. */
9408 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9412 tg3_write_mem(tp,
9415 tg3_write_mem(tp,
9418 tg3_write_mem(tp,
9422 if (!tg3_flag(tp, 5705_PLUS))
9423 tg3_write_mem(tp,
9429 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9433 if (!tg3_flag(tp, ENABLE_TSS)) {
9442 for (; i < tp->txq_cnt; i++) {
9454 for (; i < tp->irq_max - 1; i++) {
9461 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9464 u32 limit = tp->rxq_cnt;
9466 if (!tg3_flag(tp, ENABLE_RSS)) {
9488 for (; i < tp->irq_max - 1; i++) {
9495 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9497 tg3_coal_tx_init(tp, ec);
9498 tg3_coal_rx_init(tp, ec);
9500 if (!tg3_flag(tp, 5705_PLUS)) {
9506 if (!tp->link_up)
9513 /* tp->lock is held. */
9514 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9519 if (!tg3_flag(tp, 5705_PLUS))
9521 else if (tg3_flag(tp, 5717_PLUS))
9523 else if (tg3_flag(tp, 57765_CLASS) ||
9524 tg3_asic_rev(tp) == ASIC_REV_5762)
9531 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9535 /* tp->lock is held. */
9536 static void tg3_tx_rcbs_init(struct tg3 *tp)
9541 if (tg3_flag(tp, ENABLE_TSS))
9544 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9545 struct tg3_napi *tnapi = &tp->napi[i];
9550 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9556 /* tp->lock is held. */
9557 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9562 if (tg3_flag(tp, 5717_PLUS))
9564 else if (!tg3_flag(tp, 5705_PLUS))
9566 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9567 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9568 tg3_flag(tp, 57765_CLASS))
9575 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9579 /* tp->lock is held. */
9580 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9585 if (tg3_flag(tp, ENABLE_RSS))
9588 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9589 struct tg3_napi *tnapi = &tp->napi[i];
9594 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9595 (tp->rx_ret_ring_mask + 1) <<
9600 /* tp->lock is held. */
9601 static void tg3_rings_reset(struct tg3 *tp)
9605 struct tg3_napi *tnapi = &tp->napi[0];
9607 tg3_tx_rcbs_disable(tp);
9609 tg3_rx_ret_rcbs_disable(tp);
9612 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9613 tp->napi[0].chk_msi_cnt = 0;
9614 tp->napi[0].last_rx_cons = 0;
9615 tp->napi[0].last_tx_cons = 0;
9618 if (tg3_flag(tp, SUPPORT_MSIX)) {
9619 for (i = 1; i < tp->irq_max; i++) {
9620 tp->napi[i].tx_prod = 0;
9621 tp->napi[i].tx_cons = 0;
9622 if (tg3_flag(tp, ENABLE_TSS))
9623 tw32_mailbox(tp->napi[i].prodmbox, 0);
9624 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9625 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9626 tp->napi[i].chk_msi_cnt = 0;
9627 tp->napi[i].last_rx_cons = 0;
9628 tp->napi[i].last_tx_cons = 0;
9630 if (!tg3_flag(tp, ENABLE_TSS))
9631 tw32_mailbox(tp->napi[0].prodmbox, 0);
9633 tp->napi[0].tx_prod = 0;
9634 tp->napi[0].tx_cons = 0;
9635 tw32_mailbox(tp->napi[0].prodmbox, 0);
9636 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9640 if (!tg3_flag(tp, 5705_PLUS)) {
9657 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9667 tg3_tx_rcbs_init(tp);
9668 tg3_rx_ret_rcbs_init(tp);
9671 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9675 if (!tg3_flag(tp, 5750_PLUS) ||
9676 tg3_flag(tp, 5780_CLASS) ||
9677 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9678 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9679 tg3_flag(tp, 57765_PLUS))
9681 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9682 tg3_asic_rev(tp) == ASIC_REV_5787)
9687 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9688 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9693 if (tg3_flag(tp, 57765_PLUS))
9696 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9701 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9706 if (tg3_flag(tp, 57765_PLUS))
9734 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9745 struct tg3 *tp = netdev_priv(dev);
9748 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9755 if (!tg3_flag(tp, ENABLE_ASF))
9764 tg3_set_multi(tp, 1);
9767 tg3_set_multi(tp, 0);
9790 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9798 __tg3_set_one_mac_addr(tp, ha->addr,
9799 i + TG3_UCAST_ADDR_IDX(tp));
9804 if (rx_mode != tp->rx_mode) {
9805 tp->rx_mode = rx_mode;
9811 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9816 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9819 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9823 if (!tg3_flag(tp, SUPPORT_MSIX))
9826 if (tp->rxq_cnt == 1) {
9827 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9833 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9838 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9841 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9847 u32 val = tp->rss_ind_tbl[i];
9851 val |= tp->rss_ind_tbl[i];
9858 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9860 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9866 /* tp->lock is held. */
9867 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9871 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9873 tg3_disable_ints(tp);
9875 tg3_stop_fw(tp);
9877 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9879 if (tg3_flag(tp, INIT_COMPLETE))
9880 tg3_abort_hw(tp, 1);
9882 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9883 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9884 tg3_phy_pull_config(tp);
9885 tg3_eee_pull_config(tp, NULL);
9886 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9890 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9891 tg3_setup_eee(tp);
9894 tg3_phy_reset(tp);
9896 err = tg3_chip_reset(tp);
9900 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9902 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9923 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9938 if (tg3_flag(tp, L1PLLPD_EN)) {
9952 if (tg3_flag(tp, 57765_CLASS)) {
9953 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9968 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
10002 if (!tg3_flag(tp, CPMU_PRESENT)) {
10003 if (!tg3_flag(tp, PCI_EXPRESS))
10004 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
10005 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
10008 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
10009 tg3_flag(tp, PCIX_MODE)) {
10015 if (tg3_flag(tp, ENABLE_APE)) {
10026 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
10038 err = tg3_init_rings(tp);
10042 if (tg3_flag(tp, 57765_PLUS)) {
10045 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
10047 if (!tg3_flag(tp, 57765_CLASS) &&
10048 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10049 tg3_asic_rev(tp) != ASIC_REV_5762)
10051 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10052 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
10053 tg3_asic_rev(tp) != ASIC_REV_5761) {
10057 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10060 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10064 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10072 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10075 if (tp->rxptpctl)
10077 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10079 if (tg3_flag(tp, PTP_CAPABLE))
10082 tw32(GRC_MODE, tp->grc_mode | val);
10088 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10089 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {
10101 if (tg3_flag(tp, 5750_PLUS)) {
10103 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10105 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10111 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10114 fw_len = tp->fw_len;
10122 if (tp->dev->mtu <= ETH_DATA_LEN) {
10124 tp->bufmgr_config.mbuf_read_dma_low_water);
10126 tp->bufmgr_config.mbuf_mac_rx_low_water);
10128 tp->bufmgr_config.mbuf_high_water);
10131 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10133 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10135 tp->bufmgr_config.mbuf_high_water_jumbo);
10138 tp->bufmgr_config.dma_low_water);
10140 tp->bufmgr_config.dma_high_water);
10143 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10145 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10146 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10147 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10148 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10157 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10161 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10164 tg3_setup_rxbd_thresholds(tp);
10187 if (!tg3_flag(tp, 5717_PLUS))
10192 if (!tg3_flag(tp, 5705_PLUS))
10199 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10200 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10202 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10207 val = TG3_RX_JMB_RING_SIZE(tp) <<
10211 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10212 tg3_flag(tp, 57765_CLASS) ||
10213 tg3_asic_rev(tp) == ASIC_REV_5762)
10221 if (tg3_flag(tp, 57765_PLUS)) {
10222 val = TG3_RX_STD_RING_SIZE(tp);
10232 tpr->rx_std_prod_idx = tp->rx_pending;
10236 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10239 tg3_rings_reset(tp);
10242 __tg3_set_mac_addr(tp, false);
10246 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10255 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10256 tg3_asic_rev(tp) == ASIC_REV_5762)
10276 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10279 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10280 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10281 tg3_asic_rev(tp) == ASIC_REV_57780)
10286 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10287 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10288 if (tg3_flag(tp, TSO_CAPABLE)) {
10291 !tg3_flag(tp, IS_5788)) {
10296 if (tg3_flag(tp, PCI_EXPRESS))
10299 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10300 tp->dma_limit = 0;
10301 if (tp->dev->mtu <= ETH_DATA_LEN) {
10303 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10307 if (tg3_flag(tp, HW_TSO_1) ||
10308 tg3_flag(tp, HW_TSO_2) ||
10309 tg3_flag(tp, HW_TSO_3))
10312 if (tg3_flag(tp, 57765_PLUS) ||
10313 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10314 tg3_asic_rev(tp) == ASIC_REV_57780)
10317 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10318 tg3_asic_rev(tp) == ASIC_REV_5762)
10321 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10322 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10323 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10324 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10325 tg3_flag(tp, 57765_PLUS)) {
10328 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10334 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10335 tg3_asic_rev(tp) == ASIC_REV_5762) {
10346 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10347 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10348 tg3_asic_rev(tp) == ASIC_REV_5762) {
10351 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10363 if (tg3_flag(tp, 5750_PLUS)) {
10368 tg3_flag(tp, TSO_CAPABLE)) {
10389 __tg3_set_coalesce(tp, &tp->coal);
10391 if (!tg3_flag(tp, 5705_PLUS)) {
10397 ((u64) tp->stats_mapping >> 32));
10399 ((u64) tp->stats_mapping & 0xffffffff));
10408 tg3_write_mem(tp, i, 0);
10413 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10417 if (!tg3_flag(tp, 5705_PLUS))
10420 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10421 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10427 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10430 if (tg3_flag(tp, ENABLE_APE))
10431 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10432 if (!tg3_flag(tp, 5705_PLUS) &&
10433 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10434 tg3_asic_rev(tp) != ASIC_REV_5700)
10435 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10436 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10439 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10445 if (!tg3_flag(tp, IS_NIC)) {
10452 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10456 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10459 tp->grc_local_ctrl &= ~gpio_mask;
10460 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10463 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10464 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10467 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10470 if (tg3_flag(tp, USING_MSIX)) {
10473 if (tp->irq_cnt > 1)
10475 if (!tg3_flag(tp, 1SHOT_MSI))
10480 if (!tg3_flag(tp, 5705_PLUS)) {
10491 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10492 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10493 if (tg3_flag(tp, TSO_CAPABLE) &&
10494 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10495 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10498 !tg3_flag(tp, IS_5788)) {
10504 if (tg3_flag(tp, 5755_PLUS))
10507 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10513 if (tg3_flag(tp, PCIX_MODE)) {
10516 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10518 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10521 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10525 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10532 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10533 tg3_asic_rev(tp) == ASIC_REV_5720) {
10535 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10540 val |= tg3_lso_rd_dma_workaround_bit(tp);
10542 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10547 if (!tg3_flag(tp, 5705_PLUS))
10550 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10559 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10563 if (tg3_flag(tp, HW_TSO_1) ||
10564 tg3_flag(tp, HW_TSO_2) ||
10565 tg3_flag(tp, HW_TSO_3))
10568 if (tg3_flag(tp, ENABLE_TSS))
10573 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10574 err = tg3_load_5701_a0_firmware_fix(tp);
10579 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10583 tg3_load_57766_firmware(tp);
10586 if (tg3_flag(tp, TSO_CAPABLE)) {
10587 err = tg3_load_tso_firmware(tp);
10592 tp->tx_mode = TX_MODE_ENABLE;
10594 if (tg3_flag(tp, 5755_PLUS) ||
10595 tg3_asic_rev(tp) == ASIC_REV_5906)
10596 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10598 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10599 tg3_asic_rev(tp) == ASIC_REV_5762) {
10601 tp->tx_mode &= ~val;
10602 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10605 tw32_f(MAC_TX_MODE, tp->tx_mode);
10608 if (tg3_flag(tp, ENABLE_RSS)) {
10611 tg3_rss_write_indir_tbl(tp);
10619 tp->rx_mode = RX_MODE_ENABLE;
10620 if (tg3_flag(tp, 5755_PLUS))
10621 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10623 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10624 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10626 if (tg3_flag(tp, ENABLE_RSS))
10627 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10634 tw32_f(MAC_RX_MODE, tp->rx_mode);
10637 tw32(MAC_LED_CTRL, tp->led_ctrl);
10640 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10644 tw32_f(MAC_RX_MODE, tp->rx_mode);
10647 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10648 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10649 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10657 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10664 if (tg3_flag(tp, 57765_CLASS))
10670 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10671 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10673 tg3_flag_set(tp, HW_AUTONEG);
10676 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10677 tg3_asic_rev(tp) == ASIC_REV_5714) {
10682 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10683 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10684 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10687 if (!tg3_flag(tp, USE_PHYLIB)) {
10688 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10689 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10691 err = tg3_setup_phy(tp, false);
10695 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10696 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10700 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10701 tg3_writephy(tp, MII_TG3_TEST1,
10703 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10708 __tg3_set_rx_mode(tp->dev);
10716 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10720 if (tg3_flag(tp, ENABLE_ASF))
10770 if (tg3_flag(tp, ENABLE_APE))
10772 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10775 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10781 * packet processing. Invoked with tp->lock held.
10783 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10789 tg3_enable_register_access(tp);
10790 tg3_poll_fw(tp);
10792 tg3_switch_clocks(tp);
10796 return tg3_reset_hw(tp, reset_phy);
10800 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10806 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10819 struct tg3 *tp = dev_get_drvdata(dev);
10822 spin_lock_bh(&tp->lock);
10823 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10825 spin_unlock_bh(&tp->lock);
10845 static void tg3_hwmon_close(struct tg3 *tp)
10847 if (tp->hwmon_dev) {
10848 hwmon_device_unregister(tp->hwmon_dev);
10849 tp->hwmon_dev = NULL;
10853 static void tg3_hwmon_open(struct tg3 *tp)
10857 struct pci_dev *pdev = tp->pdev;
10860 tg3_sd_scan_scratchpad(tp, ocirs);
10873 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10874 tp, tg3_groups);
10875 if (IS_ERR(tp->hwmon_dev)) {
10876 tp->hwmon_dev = NULL;
10881 static inline void tg3_hwmon_close(struct tg3 *tp) { }
10882 static inline void tg3_hwmon_open(struct tg3 *tp) { }
10893 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10895 struct tg3_hw_stats *sp = tp->hw_stats;
10897 if (!tp->link_up)
10913 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10919 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10921 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10940 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10941 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10942 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10943 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10959 static void tg3_chk_missed_msi(struct tg3 *tp)
10963 for (i = 0; i < tp->irq_cnt; i++) {
10964 struct tg3_napi *tnapi = &tp->napi[i];
10984 struct tg3 *tp = from_timer(tp, t, timer);
10986 spin_lock(&tp->lock);
10988 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
10989 spin_unlock(&tp->lock);
10993 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10994 tg3_flag(tp, 57765_CLASS))
10995 tg3_chk_missed_msi(tp);
10997 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
11002 if (!tg3_flag(tp, TAGGED_STATUS)) {
11007 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
11009 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
11011 tw32(HOSTCC_MODE, tp->coalesce_mode |
11016 spin_unlock(&tp->lock);
11017 tg3_reset_task_schedule(tp);
11023 if (!--tp->timer_counter) {
11024 if (tg3_flag(tp, 5705_PLUS))
11025 tg3_periodic_fetch_stats(tp);
11027 if (tp->setlpicnt && !--tp->setlpicnt)
11028 tg3_phy_eee_enable(tp);
11030 if (tg3_flag(tp, USE_LINKCHG_REG)) {
11037 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
11044 tg3_setup_phy(tp, false);
11045 } else if (tg3_flag(tp, POLL_SERDES)) {
11049 if (tp->link_up &&
11053 if (!tp->link_up &&
11059 if (!tp->serdes_counter) {
11061 (tp->mac_mode &
11064 tw32_f(MAC_MODE, tp->mac_mode);
11067 tg3_setup_phy(tp, false);
11069 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
11070 tg3_flag(tp, 5780_CLASS)) {
11071 tg3_serdes_parallel_detect(tp);
11072 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
11077 if (link_up != tp->link_up)
11078 tg3_setup_phy(tp, false);
11081 tp->timer_counter = tp->timer_multiplier;
11101 if (!--tp->asf_counter) {
11102 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11103 tg3_wait_for_event_ack(tp);
11105 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11107 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11108 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11111 tg3_generate_fw_event(tp);
11113 tp->asf_counter = tp->asf_multiplier;
11117 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);
11119 spin_unlock(&tp->lock);
11122 tp->timer.expires = jiffies + tp->timer_offset;
11123 add_timer(&tp->timer);
11126 static void tg3_timer_init(struct tg3 *tp)
11128 if (tg3_flag(tp, TAGGED_STATUS) &&
11129 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11130 !tg3_flag(tp, 57765_CLASS))
11131 tp->timer_offset = HZ;
11133 tp->timer_offset = HZ / 10;
11135 BUG_ON(tp->timer_offset > HZ);
11137 tp->timer_multiplier = (HZ / tp->timer_offset);
11138 tp->asf_multiplier = (HZ / tp->timer_offset) *
11141 timer_setup(&tp->timer, tg3_timer, 0);
11144 static void tg3_timer_start(struct tg3 *tp)
11146 tp->asf_counter = tp->asf_multiplier;
11147 tp->timer_counter = tp->timer_multiplier;
11149 tp->timer.expires = jiffies + tp->timer_offset;
11150 add_timer(&tp->timer);
11153 static void tg3_timer_stop(struct tg3 *tp)
11155 del_timer_sync(&tp->timer);
11159 * Invoked with tp->lock held.
11161 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11162 __releases(tp->lock)
11163 __acquires(tp->lock)
11167 err = tg3_init_hw(tp, reset_phy);
11169 netdev_err(tp->dev,
11171 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11172 tg3_full_unlock(tp);
11173 tg3_timer_stop(tp);
11174 tp->irq_sync = 0;
11175 tg3_napi_enable(tp);
11176 dev_close(tp->dev);
11177 tg3_full_lock(tp, 0);
11184 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11188 tg3_full_lock(tp, 0);
11190 if (tp->pcierr_recovery || !netif_running(tp->dev) ||
11191 tp->pdev->error_state != pci_channel_io_normal) {
11192 tg3_flag_clear(tp, RESET_TASK_PENDING);
11193 tg3_full_unlock(tp);
11198 tg3_full_unlock(tp);
11200 tg3_phy_stop(tp);
11202 tg3_netif_stop(tp);
11204 tg3_full_lock(tp, 1);
11206 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11207 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11208 tp->write32_rx_mbox = tg3_write_flush_reg32;
11209 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11210 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11213 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11214 err = tg3_init_hw(tp, true);
11216 tg3_full_unlock(tp);
11217 tp->irq_sync = 0;
11218 tg3_napi_enable(tp);
11222 tg3_flag_clear(tp, RESET_TASK_PENDING);
11223 dev_close(tp->dev);
11227 tg3_netif_start(tp);
11228 tg3_full_unlock(tp);
11229 tg3_phy_start(tp);
11230 tg3_flag_clear(tp, RESET_TASK_PENDING);
11235 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11240 struct tg3_napi *tnapi = &tp->napi[irq_num];
11242 if (tp->irq_cnt == 1)
11243 name = tp->dev->name;
11248 "%s-txrx-%d", tp->dev->name, irq_num);
11251 "%s-tx-%d", tp->dev->name, irq_num);
11254 "%s-rx-%d", tp->dev->name, irq_num);
11257 "%s-%d", tp->dev->name, irq_num);
11261 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11263 if (tg3_flag(tp, 1SHOT_MSI))
11268 if (tg3_flag(tp, TAGGED_STATUS))
11276 static int tg3_test_interrupt(struct tg3 *tp)
11278 struct tg3_napi *tnapi = &tp->napi[0];
11279 struct net_device *dev = tp->dev;
11286 tg3_disable_ints(tp);
11294 if (tg3_flag(tp, 57765_PLUS)) {
11305 tg3_enable_ints(tp);
11307 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11322 if (tg3_flag(tp, 57765_PLUS) &&
11329 tg3_disable_ints(tp);
11333 err = tg3_request_irq(tp, 0);
11340 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11353 static int tg3_test_msi(struct tg3 *tp)
11358 if (!tg3_flag(tp, USING_MSI))
11364 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11365 pci_write_config_word(tp->pdev, PCI_COMMAND,
11368 err = tg3_test_interrupt(tp);
11370 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11380 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11384 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11386 pci_disable_msi(tp->pdev);
11388 tg3_flag_clear(tp, USING_MSI);
11389 tp->napi[0].irq_vec = tp->pdev->irq;
11391 err = tg3_request_irq(tp, 0);
11398 tg3_full_lock(tp, 1);
11400 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11401 err = tg3_init_hw(tp, true);
11403 tg3_full_unlock(tp);
11406 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11411 static int tg3_request_firmware(struct tg3 *tp)
11415 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11416 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11417 tp->fw_needed);
11421 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11428 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11429 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11430 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11431 tp->fw_len, tp->fw_needed);
11432 release_firmware(tp->fw);
11433 tp->fw = NULL;
11438 tp->fw_needed = NULL;
11442 static u32 tg3_irq_count(struct tg3 *tp)
11444 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11452 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11458 static bool tg3_enable_msix(struct tg3 *tp)
11463 tp->txq_cnt = tp->txq_req;
11464 tp->rxq_cnt = tp->rxq_req;
11465 if (!tp->rxq_cnt)
11466 tp->rxq_cnt = netif_get_num_default_rss_queues();
11467 if (tp->rxq_cnt > tp->rxq_max)
11468 tp->rxq_cnt = tp->rxq_max;
11474 if (!tp->txq_req)
11475 tp->txq_cnt = 1;
11477 tp->irq_cnt = tg3_irq_count(tp);
11479 for (i = 0; i < tp->irq_max; i++) {
11484 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11487 } else if (rc < tp->irq_cnt) {
11488 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11489 tp->irq_cnt, rc);
11490 tp->irq_cnt = rc;
11491 tp->rxq_cnt = max(rc - 1, 1);
11492 if (tp->txq_cnt)
11493 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11496 for (i = 0; i < tp->irq_max; i++)
11497 tp->napi[i].irq_vec = msix_ent[i].vector;
11499 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11500 pci_disable_msix(tp->pdev);
11504 if (tp->irq_cnt == 1)
11507 tg3_flag_set(tp, ENABLE_RSS);
11509 if (tp->txq_cnt > 1)
11510 tg3_flag_set(tp, ENABLE_TSS);
11512 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11517 static void tg3_ints_init(struct tg3 *tp)
11519 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11520 !tg3_flag(tp, TAGGED_STATUS)) {
11524 netdev_warn(tp->dev,
11529 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11530 tg3_flag_set(tp, USING_MSIX);
11531 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11532 tg3_flag_set(tp, USING_MSI);
11534 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11536 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11538 if (!tg3_flag(tp, 1SHOT_MSI))
11543 if (!tg3_flag(tp, USING_MSIX)) {
11544 tp->irq_cnt = 1;
11545 tp->napi[0].irq_vec = tp->pdev->irq;
11548 if (tp->irq_cnt == 1) {
11549 tp->txq_cnt = 1;
11550 tp->rxq_cnt = 1;
11551 netif_set_real_num_tx_queues(tp->dev, 1);
11552 netif_set_real_num_rx_queues(tp->dev, 1);
11556 static void tg3_ints_fini(struct tg3 *tp)
11558 if (tg3_flag(tp, USING_MSIX))
11559 pci_disable_msix(tp->pdev);
11560 else if (tg3_flag(tp, USING_MSI))
11561 pci_disable_msi(tp->pdev);
11562 tg3_flag_clear(tp, USING_MSI);
11563 tg3_flag_clear(tp, USING_MSIX);
11564 tg3_flag_clear(tp, ENABLE_RSS);
11565 tg3_flag_clear(tp, ENABLE_TSS);
11568 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11571 struct net_device *dev = tp->dev;
11578 tg3_ints_init(tp);
11580 tg3_rss_check_indir_tbl(tp);
11585 err = tg3_alloc_consistent(tp);
11589 tg3_napi_init(tp);
11591 tg3_napi_enable(tp);
11593 for (i = 0; i < tp->irq_cnt; i++) {
11594 err = tg3_request_irq(tp, i);
11597 struct tg3_napi *tnapi = &tp->napi[i];
11605 tg3_full_lock(tp, 0);
11608 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11610 err = tg3_init_hw(tp, reset_phy);
11612 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11613 tg3_free_rings(tp);
11616 tg3_full_unlock(tp);
11621 if (test_irq && tg3_flag(tp, USING_MSI)) {
11622 err = tg3_test_msi(tp);
11625 tg3_full_lock(tp, 0);
11626 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11627 tg3_free_rings(tp);
11628 tg3_full_unlock(tp);
11633 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11641 tg3_phy_start(tp);
11643 tg3_hwmon_open(tp);
11645 tg3_full_lock(tp, 0);
11647 tg3_timer_start(tp);
11648 tg3_flag_set(tp, INIT_COMPLETE);
11649 tg3_enable_ints(tp);
11651 tg3_ptp_resume(tp);
11653 tg3_full_unlock(tp);
11667 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11668 struct tg3_napi *tnapi = &tp->napi[i];
11673 tg3_napi_disable(tp);
11674 tg3_napi_fini(tp);
11675 tg3_free_consistent(tp);
11678 tg3_ints_fini(tp);
11683 static void tg3_stop(struct tg3 *tp)
11687 tg3_reset_task_cancel(tp);
11688 tg3_netif_stop(tp);
11690 tg3_timer_stop(tp);
11692 tg3_hwmon_close(tp);
11694 tg3_phy_stop(tp);
11696 tg3_full_lock(tp, 1);
11698 tg3_disable_ints(tp);
11700 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11701 tg3_free_rings(tp);
11702 tg3_flag_clear(tp, INIT_COMPLETE);
11704 tg3_full_unlock(tp);
11706 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11707 struct tg3_napi *tnapi = &tp->napi[i];
11711 tg3_ints_fini(tp);
11713 tg3_napi_fini(tp);
11715 tg3_free_consistent(tp);
11720 struct tg3 *tp = netdev_priv(dev);
11723 if (tp->pcierr_recovery) {
11729 if (tp->fw_needed) {
11730 err = tg3_request_firmware(tp);
11731 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11733 netdev_warn(tp->dev, "EEE capability disabled\n");
11734 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11735 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11736 netdev_warn(tp->dev, "EEE capability restored\n");
11737 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11739 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11743 netdev_warn(tp->dev, "TSO capability disabled\n");
11744 tg3_flag_clear(tp, TSO_CAPABLE);
11745 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11746 netdev_notice(tp->dev, "TSO capability restored\n");
11747 tg3_flag_set(tp, TSO_CAPABLE);
11751 tg3_carrier_off(tp);
11753 err = tg3_power_up(tp);
11757 tg3_full_lock(tp, 0);
11759 tg3_disable_ints(tp);
11760 tg3_flag_clear(tp, INIT_COMPLETE);
11762 tg3_full_unlock(tp);
11764 err = tg3_start(tp,
11765 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11768 tg3_frob_aux_power(tp, false);
11769 pci_set_power_state(tp->pdev, PCI_D3hot);
11777 struct tg3 *tp = netdev_priv(dev);
11779 if (tp->pcierr_recovery) {
11785 tg3_stop(tp);
11787 if (pci_device_is_present(tp->pdev)) {
11788 tg3_power_down_prepare(tp);
11790 tg3_carrier_off(tp);
11800 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11802 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11804 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11805 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11806 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11809 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11810 tg3_writephy(tp, MII_TG3_TEST1,
11812 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11816 tp->phy_crc_errors += val;
11818 return tp->phy_crc_errors;
11828 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11830 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11831 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11912 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11914 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11915 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11960 tg3_calc_crc_errors(tp);
11976 for (i = 0; i < tp->irq_cnt; i++) {
11977 struct tg3_napi *tnapi = &tp->napi[i];
11995 struct tg3 *tp = netdev_priv(dev);
12001 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
12004 tg3_full_lock(tp, 0);
12006 tg3_dump_legacy_regs(tp, (u32 *)_p);
12008 tg3_full_unlock(tp);
12013 struct tg3 *tp = netdev_priv(dev);
12015 return tp->nvram_size;
12020 struct tg3 *tp = netdev_priv(dev);
12026 if (tg3_flag(tp, NO_NVRAM))
12036 if (tg3_flag(tp, CPMU_PRESENT)) {
12046 tg3_override_clk(tp);
12056 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
12068 ret = tg3_nvram_read_be32(tp, offset + i, &val);
12092 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12102 tg3_restore_clk(tp);
12111 struct tg3 *tp = netdev_priv(dev);
12117 if (tg3_flag(tp, NO_NVRAM) ||
12126 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12140 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12157 ret = tg3_nvram_write_block(tp, offset, len, buf);
12168 struct tg3 *tp = netdev_priv(dev);
12171 if (tg3_flag(tp, USE_PHYLIB)) {
12173 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12175 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12183 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12187 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12201 advertising = tp->link_config.advertising;
12202 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12203 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12204 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12210 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12217 if (netif_running(dev) && tp->link_up) {
12218 cmd->base.speed = tp->link_config.active_speed;
12219 cmd->base.duplex = tp->link_config.active_duplex;
12222 tp->link_config.rmt_adv);
12224 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12225 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12235 cmd->base.phy_address = tp->phy_addr;
12236 cmd->base.autoneg = tp->link_config.autoneg;
12243 struct tg3 *tp = netdev_priv(dev);
12247 if (tg3_flag(tp, USE_PHYLIB)) {
12249 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12251 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12272 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12276 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12297 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12310 tg3_full_lock(tp, 0);
12312 tp->link_config.autoneg = cmd->base.autoneg;
12314 tp->link_config.advertising = (advertising |
12316 tp->link_config.speed = SPEED_UNKNOWN;
12317 tp->link_config.duplex = DUPLEX_UNKNOWN;
12319 tp->link_config.advertising = 0;
12320 tp->link_config.speed = speed;
12321 tp->link_config.duplex = cmd->base.duplex;
12324 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12326 tg3_warn_mgmt_link_flap(tp);
12329 tg3_setup_phy(tp, true);
12331 tg3_full_unlock(tp);
12338 struct tg3 *tp = netdev_priv(dev);
12341 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12342 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12347 struct tg3 *tp = netdev_priv(dev);
12349 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12354 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12361 struct tg3 *tp = netdev_priv(dev);
12362 struct device *dp = &tp->pdev->dev;
12367 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12373 tg3_flag_set(tp, WOL_ENABLE);
12375 tg3_flag_clear(tp, WOL_ENABLE);
12382 struct tg3 *tp = netdev_priv(dev);
12383 return tp->msg_enable;
12388 struct tg3 *tp = netdev_priv(dev);
12389 tp->msg_enable = value;
12394 struct tg3 *tp = netdev_priv(dev);
12400 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12403 tg3_warn_mgmt_link_flap(tp);
12405 if (tg3_flag(tp, USE_PHYLIB)) {
12406 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12408 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
12412 spin_lock_bh(&tp->lock);
12414 tg3_readphy(tp, MII_BMCR, &bmcr);
12415 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12417 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12418 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12422 spin_unlock_bh(&tp->lock);
12433 struct tg3 *tp = netdev_priv(dev);
12435 ering->rx_max_pending = tp->rx_std_ring_mask;
12436 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12437 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12443 ering->rx_pending = tp->rx_pending;
12444 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12445 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12449 ering->tx_pending = tp->napi[0].tx_pending;
12457 struct tg3 *tp = netdev_priv(dev);
12461 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12462 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12465 (tg3_flag(tp, TSO_BUG) &&
12470 tg3_phy_stop(tp);
12471 tg3_netif_stop(tp);
12475 tg3_full_lock(tp, irq_sync);
12477 tp->rx_pending = ering->rx_pending;
12479 if (tg3_flag(tp, MAX_RXPEND_64) &&
12480 tp->rx_pending > 63)
12481 tp->rx_pending = 63;
12483 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12484 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12486 for (i = 0; i < tp->irq_max; i++)
12487 tp->napi[i].tx_pending = ering->tx_pending;
12490 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12492 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
12493 tg3_asic_rev(tp) == ASIC_REV_5719 ||
12494 tg3_asic_rev(tp) == ASIC_REV_5720)
12497 err = tg3_restart_hw(tp, reset_phy);
12499 tg3_netif_start(tp);
12502 tg3_full_unlock(tp);
12505 tg3_phy_start(tp);
12512 struct tg3 *tp = netdev_priv(dev);
12514 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12516 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12521 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12529 struct tg3 *tp = netdev_priv(dev);
12533 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12534 tg3_warn_mgmt_link_flap(tp);
12536 if (tg3_flag(tp, USE_PHYLIB)) {
12539 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12544 tp->link_config.flowctrl = 0;
12547 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12550 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12553 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12557 tg3_flag_set(tp, PAUSE_AUTONEG);
12559 tg3_flag_clear(tp, PAUSE_AUTONEG);
12561 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12574 tg3_setup_flow_control(tp, 0, 0);
12580 tg3_netif_stop(tp);
12584 tg3_full_lock(tp, irq_sync);
12587 tg3_flag_set(tp, PAUSE_AUTONEG);
12589 tg3_flag_clear(tp, PAUSE_AUTONEG);
12591 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12593 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12595 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12597 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12600 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12602 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
12603 tg3_asic_rev(tp) == ASIC_REV_5719 ||
12604 tg3_asic_rev(tp) == ASIC_REV_5720)
12607 err = tg3_restart_hw(tp, reset_phy);
12609 tg3_netif_start(tp);
12612 tg3_full_unlock(tp);
12615 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12635 struct tg3 *tp = netdev_priv(dev);
12637 if (!tg3_flag(tp, SUPPORT_MSIX))
12642 if (netif_running(tp->dev))
12643 info->data = tp->rxq_cnt;
12660 struct tg3 *tp = netdev_priv(dev);
12662 if (tg3_flag(tp, SUPPORT_MSIX))
12670 struct tg3 *tp = netdev_priv(dev);
12679 indir[i] = tp->rss_ind_tbl[i];
12687 struct tg3 *tp = netdev_priv(dev);
12701 tp->rss_ind_tbl[i] = indir[i];
12703 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12709 tg3_full_lock(tp, 0);
12710 tg3_rss_write_indir_tbl(tp);
12711 tg3_full_unlock(tp);
12719 struct tg3 *tp = netdev_priv(dev);
12722 channel->max_rx = tp->rxq_max;
12723 channel->max_tx = tp->txq_max;
12726 channel->rx_count = tp->rxq_cnt;
12727 channel->tx_count = tp->txq_cnt;
12729 if (tp->rxq_req)
12730 channel->rx_count = tp->rxq_req;
12732 channel->rx_count = min(deflt_qs, tp->rxq_max);
12734 if (tp->txq_req)
12735 channel->tx_count = tp->txq_req;
12737 channel->tx_count = min(deflt_qs, tp->txq_max);
12744 struct tg3 *tp = netdev_priv(dev);
12746 if (!tg3_flag(tp, SUPPORT_MSIX))
12749 if (channel->rx_count > tp->rxq_max ||
12750 channel->tx_count > tp->txq_max)
12753 tp->rxq_req = channel->rx_count;
12754 tp->txq_req = channel->tx_count;
12759 tg3_stop(tp);
12761 tg3_carrier_off(tp);
12763 tg3_start(tp, true, false, false);
12786 struct tg3 *tp = netdev_priv(dev);
12808 tw32(MAC_LED_CTRL, tp->led_ctrl);
12818 struct tg3 *tp = netdev_priv(dev);
12820 if (tp->hw_stats)
12821 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12826 static __be32 *tg3_vpd_readblock(struct tg3 *tp, unsigned int *vpdlen)
12833 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12840 if (tg3_nvram_read(tp, offset, &val))
12850 if (tg3_nvram_read(tp, offset + 4, &offset))
12853 offset = tg3_nvram_logical_addr(tp, offset);
12870 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12875 buf = pci_vpd_alloc(tp->pdev, vpdlen);
12897 static int tg3_test_nvram(struct tg3 *tp)
12904 if (tg3_flag(tp, NO_NVRAM))
12907 if (tg3_nvram_read(tp, 0, &magic) != 0)
12950 err = tg3_nvram_read_be32(tp, i, &buf[j]);
13041 buf = tg3_vpd_readblock(tp, &len);
13057 static int tg3_test_link(struct tg3 *tp)
13061 if (!netif_running(tp->dev))
13064 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
13070 if (tp->link_up)
13081 static int tg3_test_registers(struct tg3 *tp)
13231 if (tg3_flag(tp, 5705_PLUS)) {
13233 if (tg3_flag(tp, 5750_PLUS))
13244 if (tg3_flag(tp, IS_5788) &&
13294 if (netif_msg_hw(tp))
13295 netdev_err(tp->dev,
13301 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13311 tg3_write_mem(tp, offset + j, test_pattern[i]);
13312 tg3_read_mem(tp, offset + j, &val);
13320 static int tg3_test_memory(struct tg3 *tp)
13367 if (tg3_flag(tp, 5717_PLUS))
13369 else if (tg3_flag(tp, 57765_CLASS) ||
13370 tg3_asic_rev(tp) == ASIC_REV_5762)
13372 else if (tg3_flag(tp, 5755_PLUS))
13374 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13376 else if (tg3_flag(tp, 5705_PLUS))
13382 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13413 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13424 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13426 tnapi = &tp->napi[0];
13427 rnapi = &tp->napi[0];
13428 if (tp->irq_cnt > 1) {
13429 if (tg3_flag(tp, ENABLE_RSS))
13430 rnapi = &tp->napi[1];
13431 if (tg3_flag(tp, ENABLE_TSS))
13432 tnapi = &tp->napi[1];
13439 skb = netdev_alloc_skb(tp->dev, tx_len);
13444 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13468 if (tg3_flag(tp, HW_TSO_1) ||
13469 tg3_flag(tp, HW_TSO_2) ||
13470 tg3_flag(tp, HW_TSO_3)) {
13478 if (tg3_flag(tp, HW_TSO_3)) {
13483 } else if (tg3_flag(tp, HW_TSO_2))
13485 else if (tg3_flag(tp, HW_TSO_1) ||
13486 tg3_asic_rev(tp) == ASIC_REV_5705) {
13497 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13505 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE);
13506 if (dma_mapping_error(&tp->pdev->dev, map)) {
13515 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13542 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13604 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len,
13607 rx_data += TG3_RX_OFFSET(tp);
13629 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13635 if (tp->dma_limit)
13636 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13638 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13639 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13641 if (!netif_running(tp->dev)) {
13649 err = tg3_reset_hw(tp, true);
13658 if (tg3_flag(tp, ENABLE_RSS)) {
13672 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13673 !tg3_flag(tp, CPMU_PRESENT)) {
13674 tg3_mac_loopback(tp, true);
13676 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13679 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13680 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13683 tg3_mac_loopback(tp, false);
13686 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13687 !tg3_flag(tp, USE_PHYLIB)) {
13690 tg3_phy_lpbk_set(tp, 0, false);
13699 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13701 if (tg3_flag(tp, TSO_CAPABLE) &&
13702 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13704 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13705 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13709 tg3_phy_lpbk_set(tp, 0, true);
13717 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13720 if (tg3_flag(tp, TSO_CAPABLE) &&
13721 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13724 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13725 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13731 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13732 tg3_phy_toggle_apd(tp, true);
13739 tp->phy_flags |= eee_cap;
13747 struct tg3 *tp = netdev_priv(dev);
13750 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13751 if (tg3_power_up(tp)) {
13756 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13761 if (tg3_test_nvram(tp) != 0) {
13765 if (!doextlpbk && tg3_test_link(tp)) {
13773 tg3_phy_stop(tp);
13774 tg3_netif_stop(tp);
13778 tg3_full_lock(tp, irq_sync);
13779 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13780 err = tg3_nvram_lock(tp);
13781 tg3_halt_cpu(tp, RX_CPU_BASE);
13782 if (!tg3_flag(tp, 5705_PLUS))
13783 tg3_halt_cpu(tp, TX_CPU_BASE);
13785 tg3_nvram_unlock(tp);
13787 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13788 tg3_phy_reset(tp);
13790 if (tg3_test_registers(tp) != 0) {
13795 if (tg3_test_memory(tp) != 0) {
13803 if (tg3_test_loopback(tp, data, doextlpbk))
13806 tg3_full_unlock(tp);
13808 if (tg3_test_interrupt(tp) != 0) {
13813 tg3_full_lock(tp, 0);
13815 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13817 tg3_flag_set(tp, INIT_COMPLETE);
13818 err2 = tg3_restart_hw(tp, true);
13820 tg3_netif_start(tp);
13823 tg3_full_unlock(tp);
13826 tg3_phy_start(tp);
13828 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13829 tg3_power_down_prepare(tp);
13835 struct tg3 *tp = netdev_priv(dev);
13838 if (!tg3_flag(tp, PTP_CAPABLE))
13850 tp->rxptpctl = 0;
13853 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13857 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13861 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13865 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13869 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13873 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13877 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13881 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13885 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13889 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13893 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13897 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13904 if (netif_running(dev) && tp->rxptpctl)
13906 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13909 tg3_flag_set(tp, TX_TSTAMP_EN);
13911 tg3_flag_clear(tp, TX_TSTAMP_EN);
13919 struct tg3 *tp = netdev_priv(dev);
13922 if (!tg3_flag(tp, PTP_CAPABLE))
13926 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13929 switch (tp->rxptpctl) {
13981 struct tg3 *tp = netdev_priv(dev);
13984 if (tg3_flag(tp, USE_PHYLIB)) {
13986 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13988 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
13994 data->phy_id = tp->phy_addr;
14000 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14006 spin_lock_bh(&tp->lock);
14007 err = __tg3_readphy(tp, data->phy_id & 0x1f,
14009 spin_unlock_bh(&tp->lock);
14017 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14023 spin_lock_bh(&tp->lock);
14024 err = __tg3_writephy(tp, data->phy_id & 0x1f,
14026 spin_unlock_bh(&tp->lock);
14048 struct tg3 *tp = netdev_priv(dev);
14050 memcpy(ec, &tp->coal, sizeof(*ec));
14059 struct tg3 *tp = netdev_priv(dev);
14063 if (!tg3_flag(tp, 5705_PLUS)) {
14085 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14086 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14087 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14088 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14089 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14090 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14091 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14092 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14093 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14096 tg3_full_lock(tp, 0);
14097 __tg3_set_coalesce(tp, &tp->coal);
14098 tg3_full_unlock(tp);
14105 struct tg3 *tp = netdev_priv(dev);
14107 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14108 netdev_warn(tp->dev, "Board does not support EEE!\n");
14112 if (edata->advertised != tp->eee.advertised) {
14113 netdev_warn(tp->dev,
14119 netdev_warn(tp->dev,
14125 tp->eee = *edata;
14127 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14128 tg3_warn_mgmt_link_flap(tp);
14130 if (netif_running(tp->dev)) {
14131 tg3_full_lock(tp, 0);
14132 tg3_setup_eee(tp);
14133 tg3_phy_reset(tp);
14134 tg3_full_unlock(tp);
14142 struct tg3 *tp = netdev_priv(dev);
14144 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14145 netdev_warn(tp->dev,
14150 *edata = tp->eee;
14199 struct tg3 *tp = netdev_priv(dev);
14201 spin_lock_bh(&tp->lock);
14202 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) {
14203 *stats = tp->net_stats_prev;
14204 spin_unlock_bh(&tp->lock);
14208 tg3_get_nstats(tp, stats);
14209 spin_unlock_bh(&tp->lock);
14214 struct tg3 *tp = netdev_priv(dev);
14219 tg3_full_lock(tp, 0);
14221 tg3_full_unlock(tp);
14224 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14230 if (tg3_flag(tp, 5780_CLASS)) {
14232 tg3_flag_clear(tp, TSO_CAPABLE);
14234 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14237 if (tg3_flag(tp, 5780_CLASS)) {
14238 tg3_flag_set(tp, TSO_CAPABLE);
14241 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14247 struct tg3 *tp = netdev_priv(dev);
14255 tg3_set_mtu(dev, tp, new_mtu);
14259 tg3_phy_stop(tp);
14261 tg3_netif_stop(tp);
14263 tg3_set_mtu(dev, tp, new_mtu);
14265 tg3_full_lock(tp, 1);
14267 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14272 if (tg3_asic_rev(tp) == ASIC_REV_57766 ||
14273 tg3_asic_rev(tp) == ASIC_REV_5717 ||
14274 tg3_asic_rev(tp) == ASIC_REV_5719 ||
14275 tg3_asic_rev(tp) == ASIC_REV_5720)
14278 err = tg3_restart_hw(tp, reset_phy);
14281 tg3_netif_start(tp);
14283 tg3_full_unlock(tp);
14286 tg3_phy_start(tp);
14309 static void tg3_get_eeprom_size(struct tg3 *tp)
14313 tp->nvram_size = EEPROM_CHIP_SIZE;
14315 if (tg3_nvram_read(tp, 0, &magic) != 0)
14330 while (cursize < tp->nvram_size) {
14331 if (tg3_nvram_read(tp, cursize, &val) != 0)
14340 tp->nvram_size = cursize;
14343 static void tg3_get_nvram_size(struct tg3 *tp)
14347 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14352 tg3_get_eeprom_size(tp);
14356 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14369 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14373 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14376 static void tg3_get_nvram_info(struct tg3 *tp)
14382 tg3_flag_set(tp, FLASH);
14388 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14389 tg3_flag(tp, 5780_CLASS)) {
14392 tp->nvram_jedecnum = JEDEC_ATMEL;
14393 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14394 tg3_flag_set(tp, NVRAM_BUFFERED);
14397 tp->nvram_jedecnum = JEDEC_ATMEL;
14398 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14401 tp->nvram_jedecnum = JEDEC_ATMEL;
14402 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14403 tg3_flag_set(tp, NVRAM_BUFFERED);
14406 tp->nvram_jedecnum = JEDEC_ST;
14407 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14408 tg3_flag_set(tp, NVRAM_BUFFERED);
14411 tp->nvram_jedecnum = JEDEC_SAIFUN;
14412 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14416 tp->nvram_jedecnum = JEDEC_SST;
14417 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14421 tp->nvram_jedecnum = JEDEC_ATMEL;
14422 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14423 tg3_flag_set(tp, NVRAM_BUFFERED);
14427 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14431 tp->nvram_pagesize = 256;
14434 tp->nvram_pagesize = 512;
14437 tp->nvram_pagesize = 1024;
14440 tp->nvram_pagesize = 2048;
14443 tp->nvram_pagesize = 4096;
14446 tp->nvram_pagesize = 264;
14449 tp->nvram_pagesize = 528;
14454 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14462 tg3_flag_set(tp, PROTECTED_NVRAM);
14467 tp->nvram_jedecnum = JEDEC_ATMEL;
14468 tg3_flag_set(tp, NVRAM_BUFFERED);
14471 tp->nvram_jedecnum = JEDEC_ATMEL;
14472 tg3_flag_set(tp, NVRAM_BUFFERED);
14473 tg3_flag_set(tp, FLASH);
14478 tp->nvram_jedecnum = JEDEC_ST;
14479 tg3_flag_set(tp, NVRAM_BUFFERED);
14480 tg3_flag_set(tp, FLASH);
14484 if (tg3_flag(tp, FLASH)) {
14485 tg3_nvram_get_pagesize(tp, nvcfg1);
14488 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14495 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14503 tg3_flag_set(tp, PROTECTED_NVRAM);
14513 tp->nvram_jedecnum = JEDEC_ATMEL;
14514 tg3_flag_set(tp, NVRAM_BUFFERED);
14515 tg3_flag_set(tp, FLASH);
14516 tp->nvram_pagesize = 264;
14519 tp->nvram_size = (protect ? 0x3e200 :
14522 tp->nvram_size = (protect ? 0x1f200 :
14525 tp->nvram_size = (protect ? 0x1f200 :
14531 tp->nvram_jedecnum = JEDEC_ST;
14532 tg3_flag_set(tp, NVRAM_BUFFERED);
14533 tg3_flag_set(tp, FLASH);
14534 tp->nvram_pagesize = 256;
14536 tp->nvram_size = (protect ?
14540 tp->nvram_size = (protect ?
14544 tp->nvram_size = (protect ?
14551 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14562 tp->nvram_jedecnum = JEDEC_ATMEL;
14563 tg3_flag_set(tp, NVRAM_BUFFERED);
14564 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14573 tp->nvram_jedecnum = JEDEC_ATMEL;
14574 tg3_flag_set(tp, NVRAM_BUFFERED);
14575 tg3_flag_set(tp, FLASH);
14576 tp->nvram_pagesize = 264;
14581 tp->nvram_jedecnum = JEDEC_ST;
14582 tg3_flag_set(tp, NVRAM_BUFFERED);
14583 tg3_flag_set(tp, FLASH);
14584 tp->nvram_pagesize = 256;
14589 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14597 tg3_flag_set(tp, PROTECTED_NVRAM);
14611 tp->nvram_jedecnum = JEDEC_ATMEL;
14612 tg3_flag_set(tp, NVRAM_BUFFERED);
14613 tg3_flag_set(tp, FLASH);
14614 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14615 tp->nvram_pagesize = 256;
14625 tp->nvram_jedecnum = JEDEC_ST;
14626 tg3_flag_set(tp, NVRAM_BUFFERED);
14627 tg3_flag_set(tp, FLASH);
14628 tp->nvram_pagesize = 256;
14633 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14640 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14646 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14652 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14658 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14664 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14666 tp->nvram_jedecnum = JEDEC_ATMEL;
14667 tg3_flag_set(tp, NVRAM_BUFFERED);
14668 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14671 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14680 tp->nvram_jedecnum = JEDEC_ATMEL;
14681 tg3_flag_set(tp, NVRAM_BUFFERED);
14682 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14694 tp->nvram_jedecnum = JEDEC_ATMEL;
14695 tg3_flag_set(tp, NVRAM_BUFFERED);
14696 tg3_flag_set(tp, FLASH);
14702 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14706 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14710 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14717 tp->nvram_jedecnum = JEDEC_ST;
14718 tg3_flag_set(tp, NVRAM_BUFFERED);
14719 tg3_flag_set(tp, FLASH);
14723 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14726 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14729 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14734 tg3_flag_set(tp, NO_NVRAM);
14738 tg3_nvram_get_pagesize(tp, nvcfg1);
14739 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14740 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14744 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14753 tp->nvram_jedecnum = JEDEC_ATMEL;
14754 tg3_flag_set(tp, NVRAM_BUFFERED);
14755 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14767 tp->nvram_jedecnum = JEDEC_ATMEL;
14768 tg3_flag_set(tp, NVRAM_BUFFERED);
14769 tg3_flag_set(tp, FLASH);
14777 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14780 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14794 tp->nvram_jedecnum = JEDEC_ST;
14795 tg3_flag_set(tp, NVRAM_BUFFERED);
14796 tg3_flag_set(tp, FLASH);
14805 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14808 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14813 tg3_flag_set(tp, NO_NVRAM);
14817 tg3_nvram_get_pagesize(tp, nvcfg1);
14818 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14819 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14822 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14829 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14831 tg3_flag_set(tp, NO_NVRAM);
14841 tp->nvram_pagesize = 4096;
14842 tp->nvram_jedecnum = JEDEC_MACRONIX;
14843 tg3_flag_set(tp, NVRAM_BUFFERED);
14844 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14845 tg3_flag_set(tp, FLASH);
14847 tp->nvram_size =
14871 tp->nvram_jedecnum = JEDEC_ATMEL;
14872 tg3_flag_set(tp, NVRAM_BUFFERED);
14877 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14879 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14893 tp->nvram_jedecnum = JEDEC_ATMEL;
14894 tg3_flag_set(tp, NVRAM_BUFFERED);
14895 tg3_flag_set(tp, FLASH);
14901 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14906 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14910 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14913 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14914 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14936 tp->nvram_jedecnum = JEDEC_ST;
14937 tg3_flag_set(tp, NVRAM_BUFFERED);
14938 tg3_flag_set(tp, FLASH);
14945 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14951 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14957 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14960 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14961 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14966 tg3_flag_set(tp, NO_NVRAM);
14970 tg3_nvram_get_pagesize(tp, nvcfg1);
14971 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14972 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14974 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14977 if (tg3_nvram_read(tp, 0, &val))
14982 tg3_flag_set(tp, NO_NVRAM);
14987 static void tg3_nvram_init(struct tg3 *tp)
14989 if (tg3_flag(tp, IS_SSB_CORE)) {
14991 tg3_flag_clear(tp, NVRAM);
14992 tg3_flag_clear(tp, NVRAM_BUFFERED);
14993 tg3_flag_set(tp, NO_NVRAM);
15009 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15010 tg3_asic_rev(tp) != ASIC_REV_5701) {
15011 tg3_flag_set(tp, NVRAM);
15013 if (tg3_nvram_lock(tp)) {
15014 netdev_warn(tp->dev,
15019 tg3_enable_nvram_access(tp);
15021 tp->nvram_size = 0;
15023 if (tg3_asic_rev(tp) == ASIC_REV_5752)
15024 tg3_get_5752_nvram_info(tp);
15025 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
15026 tg3_get_5755_nvram_info(tp);
15027 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
15028 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15029 tg3_asic_rev(tp) == ASIC_REV_5785)
15030 tg3_get_5787_nvram_info(tp);
15031 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
15032 tg3_get_5761_nvram_info(tp);
15033 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
15034 tg3_get_5906_nvram_info(tp);
15035 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
15036 tg3_flag(tp, 57765_CLASS))
15037 tg3_get_57780_nvram_info(tp);
15038 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15039 tg3_asic_rev(tp) == ASIC_REV_5719)
15040 tg3_get_5717_nvram_info(tp);
15041 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
15042 tg3_asic_rev(tp) == ASIC_REV_5762)
15043 tg3_get_5720_nvram_info(tp);
15045 tg3_get_nvram_info(tp);
15047 if (tp->nvram_size == 0)
15048 tg3_get_nvram_size(tp);
15050 tg3_disable_nvram_access(tp);
15051 tg3_nvram_unlock(tp);
15054 tg3_flag_clear(tp, NVRAM);
15055 tg3_flag_clear(tp, NVRAM_BUFFERED);
15057 tg3_get_eeprom_size(tp);
15130 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15136 tp->pdev->subsystem_vendor) &&
15138 tp->pdev->subsystem_device))
15144 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15148 tp->phy_id = TG3_PHY_ID_INVALID;
15149 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15152 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15153 tg3_flag_set(tp, WOL_CAP);
15155 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15157 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15158 tg3_flag_set(tp, IS_NIC);
15162 tg3_flag_set(tp, ASPM_WORKAROUND);
15165 tg3_flag_set(tp, WOL_ENABLE);
15166 device_set_wakeup_enable(&tp->pdev->dev, true);
15171 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15178 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15179 tp->nic_sram_data_cfg = nic_cfg;
15181 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15183 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15184 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15185 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15187 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15189 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15190 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15192 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15193 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15194 tg3_asic_rev(tp) == ASIC_REV_5720)
15195 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15201 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15212 tp->phy_id = eeprom_phy_id;
15214 if (!tg3_flag(tp, 5705_PLUS))
15215 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15217 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15220 if (tg3_flag(tp, 5750_PLUS))
15229 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15233 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15237 tp->led_ctrl = LED_CTRL_MODE_MAC;
15242 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15243 tg3_asic_rev(tp) == ASIC_REV_5701)
15244 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15249 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15250 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15251 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15252 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15255 if (tg3_flag(tp, 5717_PLUS) ||
15256 tg3_asic_rev(tp) == ASIC_REV_5762)
15257 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15263 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15267 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15268 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15269 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15275 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15276 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15277 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15278 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15280 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15281 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15284 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15285 if ((tp->pdev->subsystem_vendor ==
15287 (tp->pdev->subsystem_device == 0x205a ||
15288 tp->pdev->subsystem_device == 0x2063))
15289 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15291 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15292 tg3_flag_set(tp, IS_NIC);
15296 tg3_flag_set(tp, ENABLE_ASF);
15297 if (tg3_flag(tp, 5750_PLUS))
15298 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15302 tg3_flag(tp, 5750_PLUS))
15303 tg3_flag_set(tp, ENABLE_APE);
15305 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15307 tg3_flag_clear(tp, WOL_CAP);
15309 if (tg3_flag(tp, WOL_CAP) &&
15311 tg3_flag_set(tp, WOL_ENABLE);
15312 device_set_wakeup_enable(&tp->pdev->dev, true);
15316 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15321 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15323 if ((tg3_flag(tp, 57765_PLUS) ||
15324 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15325 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15327 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15329 if (tg3_flag(tp, PCI_EXPRESS)) {
15332 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15333 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15334 !tg3_flag(tp, 57765_PLUS) &&
15336 tg3_flag_set(tp, ASPM_WORKAROUND);
15338 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15340 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15344 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15346 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15348 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15351 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15354 if (tg3_flag(tp, WOL_CAP))
15355 device_set_wakeup_enable(&tp->pdev->dev,
15356 tg3_flag(tp, WOL_ENABLE));
15358 device_set_wakeup_capable(&tp->pdev->dev, false);
15361 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15366 err = tg3_nvram_lock(tp);
15370 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15371 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15373 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15377 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15379 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15385 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15387 tg3_nvram_unlock(tp);
15394 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15417 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15423 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15428 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15435 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15443 static void tg3_phy_init_link_config(struct tg3 *tp)
15447 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15448 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15453 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15462 tp->link_config.advertising = adv;
15463 tp->link_config.speed = SPEED_UNKNOWN;
15464 tp->link_config.duplex = DUPLEX_UNKNOWN;
15465 tp->link_config.autoneg = AUTONEG_ENABLE;
15466 tp->link_config.active_speed = SPEED_UNKNOWN;
15467 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15469 tp->old_link = -1;
15472 static int tg3_phy_probe(struct tg3 *tp)
15479 tg3_flag_set(tp, PAUSE_AUTONEG);
15480 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15482 if (tg3_flag(tp, ENABLE_APE)) {
15483 switch (tp->pci_fn) {
15485 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15488 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15491 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15494 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15499 if (!tg3_flag(tp, ENABLE_ASF) &&
15500 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15501 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15502 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15505 if (tg3_flag(tp, USE_PHYLIB))
15506 return tg3_phy_init(tp);
15512 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15520 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15521 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15531 tp->phy_id = hw_phy_id;
15533 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15535 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15537 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15547 p = tg3_lookup_by_subsys(tp);
15549 tp->phy_id = p->phy_id;
15550 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15561 if (!tp->phy_id ||
15562 tp->phy_id == TG3_PHY_ID_BCM8002)
15563 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15567 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15568 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15569 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15570 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15571 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15572 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15573 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15574 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15575 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15576 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15578 tp->eee.supported = SUPPORTED_100baseT_Full |
15580 tp->eee.advertised = ADVERTISED_100baseT_Full |
15582 tp->eee.eee_enabled = 1;
15583 tp->eee.tx_lpi_enabled = 1;
15584 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15587 tg3_phy_init_link_config(tp);
15589 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15590 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15591 !tg3_flag(tp, ENABLE_APE) &&
15592 !tg3_flag(tp, ENABLE_ASF)) {
15595 tg3_readphy(tp, MII_BMSR, &bmsr);
15596 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15600 err = tg3_phy_reset(tp);
15604 tg3_phy_set_wirespeed(tp);
15606 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15607 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15608 tp->link_config.flowctrl);
15610 tg3_writephy(tp, MII_BMCR,
15616 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15617 err = tg3_init_5401phy_dsp(tp);
15621 err = tg3_init_5401phy_dsp(tp);
15627 static void tg3_read_vpd(struct tg3 *tp)
15633 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15650 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15651 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i);
15662 memcpy(tp->board_part_number, &vpd_data[i], len);
15666 if (tp->board_part_number[0])
15670 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15671 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15672 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15673 strcpy(tp->board_part_number, "BCM5717");
15674 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15675 strcpy(tp->board_part_number, "BCM5718");
15678 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15679 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15680 strcpy(tp->board_part_number, "BCM57780");
15681 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15682 strcpy(tp->board_part_number, "BCM57760");
15683 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15684 strcpy(tp->board_part_number, "BCM57790");
15685 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15686 strcpy(tp->board_part_number, "BCM57788");
15689 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15690 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15691 strcpy(tp->board_part_number, "BCM57761");
15692 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15693 strcpy(tp->board_part_number, "BCM57765");
15694 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15695 strcpy(tp->board_part_number, "BCM57781");
15696 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15697 strcpy(tp->board_part_number, "BCM57785");
15698 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15699 strcpy(tp->board_part_number, "BCM57791");
15700 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15701 strcpy(tp->board_part_number, "BCM57795");
15704 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15705 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15706 strcpy(tp->board_part_number, "BCM57762");
15707 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15708 strcpy(tp->board_part_number, "BCM57766");
15709 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15710 strcpy(tp->board_part_number, "BCM57782");
15711 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15712 strcpy(tp->board_part_number, "BCM57786");
15715 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15716 strcpy(tp->board_part_number, "BCM95906");
15719 strcpy(tp->board_part_number, "none");
15723 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15727 if (tg3_nvram_read(tp, offset, &val) ||
15729 tg3_nvram_read(tp, offset + 4, &val) ||
15736 static void tg3_read_bc_ver(struct tg3 *tp)
15742 if (tg3_nvram_read(tp, 0xc, &offset) ||
15743 tg3_nvram_read(tp, 0x4, &start))
15746 offset = tg3_nvram_logical_addr(tp, offset);
15748 if (tg3_nvram_read(tp, offset, &val))
15752 if (tg3_nvram_read(tp, offset + 4, &val))
15759 dst_off = strlen(tp->fw_ver);
15763 tg3_nvram_read(tp, offset + 8, &ver_offset))
15769 if (tg3_nvram_read_be32(tp, offset + i, &v))
15772 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15777 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15783 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15788 static void tg3_read_hwsb_ver(struct tg3 *tp)
15793 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15801 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15804 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15808 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15836 if (tg3_nvram_read(tp, offset, &val))
15848 offset = strlen(tp->fw_ver);
15849 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15853 offset = strlen(tp->fw_ver);
15855 tp->fw_ver[offset] = 'a' + build - 1;
15859 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15867 if (tg3_nvram_read(tp, offset, &val))
15877 if (!tg3_flag(tp, 5705_PLUS))
15879 else if (tg3_nvram_read(tp, offset - 4, &start))
15882 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15883 !tg3_fw_img_is_valid(tp, offset) ||
15884 tg3_nvram_read(tp, offset + 8, &val))
15889 vlen = strlen(tp->fw_ver);
15891 tp->fw_ver[vlen++] = ',';
15892 tp->fw_ver[vlen++] = ' ';
15896 if (tg3_nvram_read_be32(tp, offset, &v))
15902 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15906 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15911 static void tg3_probe_ncsi(struct tg3 *tp)
15915 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15919 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15923 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15924 tg3_flag_set(tp, APE_HAS_NCSI);
15927 static void tg3_read_dash_ver(struct tg3 *tp)
15933 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15935 if (tg3_flag(tp, APE_HAS_NCSI))
15937 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15942 vlen = strlen(tp->fw_ver);
15944 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15952 static void tg3_read_otp_ver(struct tg3 *tp)
15956 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15959 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15960 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15972 vlen = strlen(tp->fw_ver);
15973 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15977 static void tg3_read_fw_ver(struct tg3 *tp)
15982 if (tp->fw_ver[0] != 0)
15985 if (tg3_flag(tp, NO_NVRAM)) {
15986 strcat(tp->fw_ver, "sb");
15987 tg3_read_otp_ver(tp);
15991 if (tg3_nvram_read(tp, 0, &val))
15995 tg3_read_bc_ver(tp);
15997 tg3_read_sb_ver(tp, val);
15999 tg3_read_hwsb_ver(tp);
16001 if (tg3_flag(tp, ENABLE_ASF)) {
16002 if (tg3_flag(tp, ENABLE_APE)) {
16003 tg3_probe_ncsi(tp);
16005 tg3_read_dash_ver(tp);
16007 tg3_read_mgmtfw_ver(tp);
16011 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
16014 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
16016 if (tg3_flag(tp, LRG_PROD_RING_CAP))
16018 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
16031 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16034 unsigned int func, devnr = tp->pdev->devfn & ~7;
16037 peer = pci_get_slot(tp->pdev->bus, devnr | func);
16038 if (peer && peer != tp->pdev)
16043 * tp->pdev in that case.
16046 peer = tp->pdev;
16059 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
16061 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
16062 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16068 tg3_flag_set(tp, CPMU_PRESENT);
16070 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16071 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16072 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16073 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16074 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16075 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16076 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16077 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16078 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16079 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16080 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16082 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16083 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16084 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16085 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16086 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16087 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16088 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16089 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16090 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16091 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16096 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16102 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16103 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16105 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16106 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16108 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16109 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16110 tg3_asic_rev(tp) == ASIC_REV_5720)
16111 tg3_flag_set(tp, 5717_PLUS);
16113 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16114 tg3_asic_rev(tp) == ASIC_REV_57766)
16115 tg3_flag_set(tp, 57765_CLASS);
16117 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16118 tg3_asic_rev(tp) == ASIC_REV_5762)
16119 tg3_flag_set(tp, 57765_PLUS);
16122 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16123 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16124 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16125 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16126 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16127 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16128 tg3_flag(tp, 57765_PLUS))
16129 tg3_flag_set(tp, 5755_PLUS);
16131 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16132 tg3_asic_rev(tp) == ASIC_REV_5714)
16133 tg3_flag_set(tp, 5780_CLASS);
16135 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16136 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16137 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16138 tg3_flag(tp, 5755_PLUS) ||
16139 tg3_flag(tp, 5780_CLASS))
16140 tg3_flag_set(tp, 5750_PLUS);
16142 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16143 tg3_flag(tp, 5750_PLUS))
16144 tg3_flag_set(tp, 5705_PLUS);
16147 static bool tg3_10_100_only_device(struct tg3 *tp,
16152 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16154 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16158 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16169 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16184 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16186 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16193 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16195 tp->misc_host_ctrl |= (misc_ctrl_reg &
16197 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16198 tp->misc_host_ctrl);
16200 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16219 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16220 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16252 tp->pdev->bus->number)) {
16253 tg3_flag_set(tp, ICH_WORKAROUND);
16260 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16282 tp->pdev->bus->number) &&
16284 tp->pdev->bus->number)) {
16285 tg3_flag_set(tp, 5701_DMA_BUG);
16298 if (tg3_flag(tp, 5780_CLASS)) {
16299 tg3_flag_set(tp, 40BIT_DMA_BUG);
16300 tp->msi_cap = tp->pdev->msi_cap;
16310 tp->pdev->bus->number) &&
16312 tp->pdev->bus->number)) {
16313 tg3_flag_set(tp, 40BIT_DMA_BUG);
16320 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16321 tg3_asic_rev(tp) == ASIC_REV_5714)
16322 tp->pdev_peer = tg3_find_peer(tp);
16325 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16327 else if (tg3_flag(tp, 57765_PLUS))
16328 tg3_flag_set(tp, HW_TSO_3);
16329 else if (tg3_flag(tp, 5755_PLUS) ||
16330 tg3_asic_rev(tp) == ASIC_REV_5906)
16331 tg3_flag_set(tp, HW_TSO_2);
16332 else if (tg3_flag(tp, 5750_PLUS)) {
16333 tg3_flag_set(tp, HW_TSO_1);
16334 tg3_flag_set(tp, TSO_BUG);
16335 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16336 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16337 tg3_flag_clear(tp, TSO_BUG);
16338 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16339 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16340 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16341 tg3_flag_set(tp, FW_TSO);
16342 tg3_flag_set(tp, TSO_BUG);
16343 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16344 tp->fw_needed = FIRMWARE_TG3TSO5;
16346 tp->fw_needed = FIRMWARE_TG3TSO;
16350 if (tg3_flag(tp, HW_TSO_1) ||
16351 tg3_flag(tp, HW_TSO_2) ||
16352 tg3_flag(tp, HW_TSO_3) ||
16353 tg3_flag(tp, FW_TSO)) {
16358 tg3_flag_set(tp, TSO_CAPABLE);
16360 tg3_flag_clear(tp, TSO_CAPABLE);
16361 tg3_flag_clear(tp, TSO_BUG);
16362 tp->fw_needed = NULL;
16365 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16366 tp->fw_needed = FIRMWARE_TG3;
16368 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16369 tp->fw_needed = FIRMWARE_TG357766;
16371 tp->irq_max = 1;
16373 if (tg3_flag(tp, 5750_PLUS)) {
16374 tg3_flag_set(tp, SUPPORT_MSI);
16375 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16376 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16377 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16378 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16379 tp->pdev_peer == tp->pdev))
16380 tg3_flag_clear(tp, SUPPORT_MSI);
16382 if (tg3_flag(tp, 5755_PLUS) ||
16383 tg3_asic_rev(tp) == ASIC_REV_5906) {
16384 tg3_flag_set(tp, 1SHOT_MSI);
16387 if (tg3_flag(tp, 57765_PLUS)) {
16388 tg3_flag_set(tp, SUPPORT_MSIX);
16389 tp->irq_max = TG3_IRQ_MAX_VECS;
16393 tp->txq_max = 1;
16394 tp->rxq_max = 1;
16395 if (tp->irq_max > 1) {
16396 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16397 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16399 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16400 tg3_asic_rev(tp) == ASIC_REV_5720)
16401 tp->txq_max = tp->irq_max - 1;
16404 if (tg3_flag(tp, 5755_PLUS) ||
16405 tg3_asic_rev(tp) == ASIC_REV_5906)
16406 tg3_flag_set(tp, SHORT_DMA_BUG);
16408 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16409 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16411 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16412 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16413 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16414 tg3_asic_rev(tp) == ASIC_REV_5762)
16415 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16417 if (tg3_flag(tp, 57765_PLUS) &&
16418 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16419 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16421 if (!tg3_flag(tp, 5705_PLUS) ||
16422 tg3_flag(tp, 5780_CLASS) ||
16423 tg3_flag(tp, USE_JUMBO_BDFLAG))
16424 tg3_flag_set(tp, JUMBO_CAPABLE);
16426 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16429 if (pci_is_pcie(tp->pdev)) {
16432 tg3_flag_set(tp, PCI_EXPRESS);
16434 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16436 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16437 tg3_flag_clear(tp, HW_TSO_2);
16438 tg3_flag_clear(tp, TSO_CAPABLE);
16440 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16441 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16442 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16443 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16444 tg3_flag_set(tp, CLKREQ_BUG);
16445 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16446 tg3_flag_set(tp, L1PLLPD_EN);
16448 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16453 tg3_flag_set(tp, PCI_EXPRESS);
16454 } else if (!tg3_flag(tp, 5705_PLUS) ||
16455 tg3_flag(tp, 5780_CLASS)) {
16456 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16457 if (!tp->pcix_cap) {
16458 dev_err(&tp->pdev->dev,
16464 tg3_flag_set(tp, PCIX_MODE);
16474 !tg3_flag(tp, PCI_EXPRESS))
16475 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16477 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16478 &tp->pci_cacheline_sz);
16479 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16480 &tp->pci_lat_timer);
16481 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16482 tp->pci_lat_timer < 64) {
16483 tp->pci_lat_timer = 64;
16484 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16485 tp->pci_lat_timer);
16491 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16495 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16502 if (tg3_flag(tp, PCIX_MODE)) {
16505 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16511 pci_read_config_dword(tp->pdev,
16512 tp->pdev->pm_cap + PCI_PM_CTRL,
16516 pci_write_config_dword(tp->pdev,
16517 tp->pdev->pm_cap + PCI_PM_CTRL,
16521 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16523 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16528 tg3_flag_set(tp, PCI_HIGH_SPEED);
16530 tg3_flag_set(tp, PCI_32BIT);
16533 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16536 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16540 tp->read32 = tg3_read32;
16541 tp->write32 = tg3_write32;
16542 tp->read32_mbox = tg3_read32;
16543 tp->write32_mbox = tg3_write32;
16544 tp->write32_tx_mbox = tg3_write32;
16545 tp->write32_rx_mbox = tg3_write32;
16548 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16549 tp->write32 = tg3_write_indirect_reg32;
16550 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16551 (tg3_flag(tp, PCI_EXPRESS) &&
16552 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16560 tp->write32 = tg3_write_flush_reg32;
16563 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16564 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16565 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16566 tp->write32_rx_mbox = tg3_write_flush_reg32;
16569 if (tg3_flag(tp, ICH_WORKAROUND)) {
16570 tp->read32 = tg3_read_indirect_reg32;
16571 tp->write32 = tg3_write_indirect_reg32;
16572 tp->read32_mbox = tg3_read_indirect_mbox;
16573 tp->write32_mbox = tg3_write_indirect_mbox;
16574 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16575 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16577 iounmap(tp->regs);
16578 tp->regs = NULL;
16580 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16582 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16584 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16585 tp->read32_mbox = tg3_read32_mbox_5906;
16586 tp->write32_mbox = tg3_write32_mbox_5906;
16587 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16588 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16591 if (tp->write32 == tg3_write_indirect_reg32 ||
16592 (tg3_flag(tp, PCIX_MODE) &&
16593 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16594 tg3_asic_rev(tp) == ASIC_REV_5701)))
16595 tg3_flag_set(tp, SRAM_USE_CONFIG);
16605 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16606 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16607 tg3_flag(tp, 5780_CLASS)) {
16608 if (tg3_flag(tp, PCIX_MODE)) {
16609 pci_read_config_dword(tp->pdev,
16610 tp->pcix_cap + PCI_X_STATUS,
16612 tp->pci_fn = val & 0x7;
16614 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16615 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16616 tg3_asic_rev(tp) == ASIC_REV_5720) {
16617 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16621 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16622 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16624 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16628 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16629 tp->write32_tx_mbox = tg3_write_flush_reg32;
16630 tp->write32_rx_mbox = tg3_write_flush_reg32;
16641 tg3_get_eeprom_hw_cfg(tp);
16643 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16644 tg3_flag_clear(tp, TSO_CAPABLE);
16645 tg3_flag_clear(tp, TSO_BUG);
16646 tp->fw_needed = NULL;
16649 if (tg3_flag(tp, ENABLE_APE)) {
16656 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16659 tg3_ape_lock_init(tp);
16660 tp->ape_hb_interval =
16664 /* Set up tp->grc_local_ctrl before calling
16669 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16670 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16671 tg3_flag(tp, EEPROM_WRITE_PROT))
16672 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16677 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16678 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16680 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16681 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16682 tg3_flag(tp, 57765_CLASS))
16683 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16685 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16688 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16689 if (tg3_flag(tp, IS_NIC))
16691 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16695 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16696 tp->grc_local_ctrl |=
16700 tg3_pwrsrc_switch_to_vmain(tp);
16705 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16706 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16709 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16710 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16711 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16712 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16713 tg3_flag_clear(tp, WOL_SPEED_100MB);
16715 tg3_flag_set(tp, WOL_SPEED_100MB);
16718 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16719 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16722 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16723 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16724 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16725 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16726 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16727 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16728 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16730 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16731 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16732 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16733 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16734 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16736 if (tg3_flag(tp, 5705_PLUS) &&
16737 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16738 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16739 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16740 !tg3_flag(tp, 57765_PLUS)) {
16741 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16742 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16743 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16744 tg3_asic_rev(tp) == ASIC_REV_5761) {
16745 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16746 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16747 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16748 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16749 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16751 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16754 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16755 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16756 tp->phy_otp = tg3_read_otp_phycfg(tp);
16757 if (tp->phy_otp == 0)
16758 tp->phy_otp = TG3_OTP_DEFAULT;
16761 if (tg3_flag(tp, CPMU_PRESENT))
16762 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16764 tp->mi_mode = MAC_MI_MODE_BASE;
16766 tp->coalesce_mode = 0;
16767 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16768 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16769 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16772 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16773 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16774 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16775 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16776 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16777 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16780 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16781 tg3_asic_rev(tp) == ASIC_REV_57780)
16782 tg3_flag_set(tp, USE_PHYLIB);
16784 err = tg3_mdio_init(tp);
16790 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16791 tg3_asic_rev(tp) == ASIC_REV_5762)
16800 tw32(GRC_MODE, val | tp->grc_mode);
16802 tg3_switch_clocks(tp);
16810 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16813 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16814 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16815 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16816 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16817 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16824 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16830 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16835 tg3_nvram_init(tp);
16838 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16839 !tg3_flag(tp, NO_NVRAM))
16840 tp->fw_needed = NULL;
16845 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16848 tg3_flag_set(tp, IS_5788);
16850 if (!tg3_flag(tp, IS_5788) &&
16851 tg3_asic_rev(tp) != ASIC_REV_5700)
16852 tg3_flag_set(tp, TAGGED_STATUS);
16853 if (tg3_flag(tp, TAGGED_STATUS)) {
16854 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16857 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16858 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16859 tp->misc_host_ctrl);
16863 if (tg3_flag(tp, ENABLE_APE))
16864 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16866 tp->mac_mode = 0;
16868 if (tg3_10_100_only_device(tp, ent))
16869 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16871 err = tg3_phy_probe(tp);
16873 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16875 tg3_mdio_fini(tp);
16878 tg3_read_vpd(tp);
16879 tg3_read_fw_ver(tp);
16881 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16882 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16884 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16885 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16887 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16894 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16895 tg3_flag_set(tp, USE_LINKCHG_REG);
16897 tg3_flag_clear(tp, USE_LINKCHG_REG);
16903 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16904 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16905 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16906 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16907 tg3_flag_set(tp, USE_LINKCHG_REG);
16911 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16912 tg3_flag_set(tp, POLL_SERDES);
16914 tg3_flag_clear(tp, POLL_SERDES);
16916 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16917 tg3_flag_set(tp, POLL_CPMU_LINK);
16919 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16920 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16921 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16922 tg3_flag(tp, PCIX_MODE)) {
16923 tp->rx_offset = NET_SKB_PAD;
16925 tp->rx_copy_thresh = ~(u16)0;
16929 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16930 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16931 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16933 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16938 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16939 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16940 tg3_asic_rev(tp) == ASIC_REV_5755)
16941 tp->rx_std_max_post = 8;
16943 if (tg3_flag(tp, ASPM_WORKAROUND))
16944 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16950 static int tg3_get_device_address(struct tg3 *tp, u8 *addr)
16956 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr))
16959 if (tg3_flag(tp, IS_SSB_CORE)) {
16960 err = ssb_gige_get_macaddr(tp->pdev, addr);
16966 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16967 tg3_flag(tp, 5780_CLASS)) {
16970 if (tg3_nvram_lock(tp))
16973 tg3_nvram_unlock(tp);
16974 } else if (tg3_flag(tp, 5717_PLUS)) {
16975 if (tp->pci_fn & 1)
16977 if (tp->pci_fn > 1)
16979 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16983 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16988 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16999 if (!tg3_flag(tp, NO_NVRAM) &&
17000 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
17001 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
17027 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
17033 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17042 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17043 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17044 !tg3_flag(tp, PCI_EXPRESS))
17057 if (tg3_flag(tp, 57765_PLUS)) {
17076 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17101 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17168 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17219 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17221 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17223 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17256 static int tg3_test_dma(struct tg3 *tp)
17262 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17269 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17272 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17274 if (tg3_flag(tp, 57765_PLUS))
17277 if (tg3_flag(tp, PCI_EXPRESS)) {
17279 tp->dma_rwctrl |= 0x00180000;
17280 } else if (!tg3_flag(tp, PCIX_MODE)) {
17281 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17282 tg3_asic_rev(tp) == ASIC_REV_5750)
17283 tp->dma_rwctrl |= 0x003f0000;
17285 tp->dma_rwctrl |= 0x003f000f;
17287 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17288 tg3_asic_rev(tp) == ASIC_REV_5704) {
17296 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17297 tg3_asic_rev(tp) == ASIC_REV_5704)
17298 tp->dma_rwctrl |= 0x8000;
17300 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17302 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17305 tp->dma_rwctrl |=
17309 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17311 tp->dma_rwctrl |= 0x00144000;
17312 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17314 tp->dma_rwctrl |= 0x00148000;
17316 tp->dma_rwctrl |= 0x001b000f;
17319 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17320 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17322 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17323 tg3_asic_rev(tp) == ASIC_REV_5704)
17324 tp->dma_rwctrl &= 0xfffffff0;
17326 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17327 tg3_asic_rev(tp) == ASIC_REV_5701) {
17329 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17341 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17344 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17347 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17348 tg3_asic_rev(tp) != ASIC_REV_5701)
17354 saved_dma_rwctrl = tp->dma_rwctrl;
17355 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17356 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17365 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17367 dev_err(&tp->pdev->dev,
17374 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17376 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17386 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17388 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17389 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17390 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17393 dev_err(&tp->pdev->dev,
17407 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17414 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17415 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17418 tp->dma_rwctrl = saved_dma_rwctrl;
17421 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17425 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17430 static void tg3_init_bufmgr_config(struct tg3 *tp)
17432 if (tg3_flag(tp, 57765_PLUS)) {
17433 tp->bufmgr_config.mbuf_read_dma_low_water =
17435 tp->bufmgr_config.mbuf_mac_rx_low_water =
17437 tp->bufmgr_config.mbuf_high_water =
17440 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17442 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17444 tp->bufmgr_config.mbuf_high_water_jumbo =
17446 } else if (tg3_flag(tp, 5705_PLUS)) {
17447 tp->bufmgr_config.mbuf_read_dma_low_water =
17449 tp->bufmgr_config.mbuf_mac_rx_low_water =
17451 tp->bufmgr_config.mbuf_high_water =
17453 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17454 tp->bufmgr_config.mbuf_mac_rx_low_water =
17456 tp->bufmgr_config.mbuf_high_water =
17460 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17462 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17464 tp->bufmgr_config.mbuf_high_water_jumbo =
17467 tp->bufmgr_config.mbuf_read_dma_low_water =
17469 tp->bufmgr_config.mbuf_mac_rx_low_water =
17471 tp->bufmgr_config.mbuf_high_water =
17474 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17476 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17478 tp->bufmgr_config.mbuf_high_water_jumbo =
17482 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17483 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17486 static char *tg3_phy_string(struct tg3 *tp)
17488 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17518 static char *tg3_bus_string(struct tg3 *tp, char *str)
17520 if (tg3_flag(tp, PCI_EXPRESS)) {
17523 } else if (tg3_flag(tp, PCIX_MODE)) {
17542 if (tg3_flag(tp, PCI_HIGH_SPEED))
17547 if (tg3_flag(tp, PCI_32BIT))
17554 static void tg3_init_coal(struct tg3 *tp)
17556 struct ethtool_coalesce *ec = &tp->coal;
17570 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17578 if (tg3_flag(tp, 5705_PLUS)) {
17589 struct tg3 *tp;
17611 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17619 tp = netdev_priv(dev);
17620 tp->pdev = pdev;
17621 tp->dev = dev;
17622 tp->rx_mode = TG3_DEF_RX_MODE;
17623 tp->tx_mode = TG3_DEF_TX_MODE;
17624 tp->irq_sync = 1;
17625 tp->pcierr_recovery = false;
17628 tp->msg_enable = tg3_debug;
17630 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17633 tg3_flag_set(tp, IS_SSB_CORE);
17635 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17637 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17639 tg3_flag_set(tp, USE_PHYLIB);
17640 tg3_flag_set(tp, ROBOSWITCH);
17643 tg3_flag_set(tp, RGMII_MODE);
17650 tp->misc_host_ctrl =
17662 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17665 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17667 spin_lock_init(&tp->lock);
17668 spin_lock_init(&tp->indirect_lock);
17669 INIT_WORK(&tp->reset_task, tg3_reset_task);
17671 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17672 if (!tp->regs) {
17678 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17679 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17680 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17681 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17682 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17683 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17684 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17685 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17687 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17688 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17689 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17690 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17691 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17692 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17693 tg3_flag_set(tp, ENABLE_APE);
17694 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17695 if (!tp->aperegs) {
17703 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17704 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17711 err = tg3_get_invariants(tp, ent);
17724 if (tg3_flag(tp, IS_5788))
17726 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17757 tg3_init_bufmgr_config(tp);
17762 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17765 if (tg3_flag(tp, 5755_PLUS))
17773 if ((tg3_flag(tp, HW_TSO_1) ||
17774 tg3_flag(tp, HW_TSO_2) ||
17775 tg3_flag(tp, HW_TSO_3)) &&
17778 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17781 if (tg3_flag(tp, HW_TSO_3) ||
17782 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17783 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17784 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17785 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17786 tg3_asic_rev(tp) == ASIC_REV_57780)
17799 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17800 !tg3_flag(tp, CPMU_PRESENT))
17809 dev->max_mtu = TG3_MAX_MTU(tp);
17811 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17812 !tg3_flag(tp, TSO_CAPABLE) &&
17814 tg3_flag_set(tp, MAX_RXPEND_64);
17815 tp->rx_pending = 63;
17818 err = tg3_get_device_address(tp, addr);
17829 for (i = 0; i < tp->irq_max; i++) {
17830 struct tg3_napi *tnapi = &tp->napi[i];
17832 tnapi->tp = tp;
17846 if (!tg3_flag(tp, SUPPORT_MSIX))
17874 tg3_full_lock(tp, 0);
17876 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17877 tg3_full_unlock(tp);
17880 err = tg3_test_dma(tp);
17886 tg3_init_coal(tp);
17890 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17891 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17892 tg3_asic_rev(tp) == ASIC_REV_5762)
17893 tg3_flag_set(tp, PTP_CAPABLE);
17895 tg3_timer_init(tp);
17897 tg3_carrier_off(tp);
17905 if (tg3_flag(tp, PTP_CAPABLE)) {
17906 tg3_ptp_init(tp);
17907 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
17908 &tp->pdev->dev);
17909 if (IS_ERR(tp->ptp_clock))
17910 tp->ptp_clock = NULL;
17914 tp->board_part_number,
17915 tg3_chip_rev_id(tp),
17916 tg3_bus_string(tp, str),
17919 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) {
17922 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17924 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17931 tg3_phy_string(tp), ethtype,
17932 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17933 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17938 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17939 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17940 tg3_flag(tp, ENABLE_ASF) != 0,
17941 tg3_flag(tp, TSO_CAPABLE) != 0);
17943 tp->dma_rwctrl,
17952 if (tp->aperegs) {
17953 iounmap(tp->aperegs);
17954 tp->aperegs = NULL;
17958 if (tp->regs) {
17959 iounmap(tp->regs);
17960 tp->regs = NULL;
17980 struct tg3 *tp = netdev_priv(dev);
17982 tg3_ptp_fini(tp);
17984 release_firmware(tp->fw);
17986 tg3_reset_task_cancel(tp);
17988 if (tg3_flag(tp, USE_PHYLIB)) {
17989 tg3_phy_fini(tp);
17990 tg3_mdio_fini(tp);
17994 if (tp->aperegs) {
17995 iounmap(tp->aperegs);
17996 tp->aperegs = NULL;
17998 if (tp->regs) {
17999 iounmap(tp->regs);
18000 tp->regs = NULL;
18012 struct tg3 *tp = netdev_priv(dev);
18020 tg3_reset_task_cancel(tp);
18021 tg3_phy_stop(tp);
18022 tg3_netif_stop(tp);
18024 tg3_timer_stop(tp);
18026 tg3_full_lock(tp, 1);
18027 tg3_disable_ints(tp);
18028 tg3_full_unlock(tp);
18032 tg3_full_lock(tp, 0);
18033 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
18034 tg3_flag_clear(tp, INIT_COMPLETE);
18035 tg3_full_unlock(tp);
18037 err = tg3_power_down_prepare(tp);
18041 tg3_full_lock(tp, 0);
18043 tg3_flag_set(tp, INIT_COMPLETE);
18044 err2 = tg3_restart_hw(tp, true);
18048 tg3_timer_start(tp);
18051 tg3_netif_start(tp);
18054 tg3_full_unlock(tp);
18057 tg3_phy_start(tp);
18068 struct tg3 *tp = netdev_priv(dev);
18078 tg3_full_lock(tp, 0);
18080 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18082 tg3_flag_set(tp, INIT_COMPLETE);
18083 err = tg3_restart_hw(tp,
18084 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18088 tg3_timer_start(tp);
18090 tg3_netif_start(tp);
18093 tg3_full_unlock(tp);
18096 tg3_phy_start(tp);
18109 struct tg3 *tp = netdev_priv(dev);
18111 tg3_reset_task_cancel(tp);
18121 tg3_power_down(tp);
18140 struct tg3 *tp = netdev_priv(netdev);
18146 tg3_reset_task_cancel(tp);
18151 if (!netdev || tp->pcierr_recovery || !netif_running(netdev))
18156 tp->pcierr_recovery = true;
18158 tg3_phy_stop(tp);
18160 tg3_netif_stop(tp);
18162 tg3_timer_stop(tp);
18167 tg3_full_lock(tp, 0);
18168 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18169 tg3_full_unlock(tp);
18174 tg3_napi_enable(tp);
18199 struct tg3 *tp = netdev_priv(netdev);
18220 err = tg3_power_up(tp);
18228 tg3_napi_enable(tp);
18246 struct tg3 *tp = netdev_priv(netdev);
18254 tg3_full_lock(tp, 0);
18255 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18256 tg3_flag_set(tp, INIT_COMPLETE);
18257 err = tg3_restart_hw(tp, true);
18259 tg3_full_unlock(tp);
18266 tg3_timer_start(tp);
18268 tg3_netif_start(tp);
18270 tg3_full_unlock(tp);
18272 tg3_phy_start(tp);
18275 tp->pcierr_recovery = false;