Lines Matching refs:tg3_writephy
1230 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1243 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1247 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1266 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1270 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1296 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1307 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1321 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1347 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1360 err = tg3_writephy(tp, MII_BMCR, phy_control);
2205 tg3_writephy(tp, MII_TG3_FET_TEST,
2212 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2214 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2263 tg3_writephy(tp, MII_TG3_FET_TEST,
2270 tg3_writephy(tp, reg, phy);
2272 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2471 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2473 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2485 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2487 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2512 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2531 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2533 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2535 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2536 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2564 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2567 tg3_writephy(tp, MII_BMCR,
2574 tg3_writephy(tp, MII_CTRL1000,
2595 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2596 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2600 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2607 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2709 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2723 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2724 tg3_writephy(tp, MII_TG3_TEST1,
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2752 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2758 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
3086 tg3_writephy(tp, MII_ADVERTISE, 0);
3087 tg3_writephy(tp, MII_BMCR,
3090 tg3_writephy(tp, MII_TG3_FET_TEST,
3094 tg3_writephy(tp,
3098 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3103 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3126 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4447 tg3_writephy(tp, MII_BMCR,
4461 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4484 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4497 tg3_writephy(tp, MII_BMCR, bmcr);
4843 tg3_writephy(tp, 0x15, 0x0a75);
4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
5459 tg3_writephy(tp, 0x16, 0x8007);
5462 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5470 tg3_writephy(tp, 0x10, 0x8411);
5473 tg3_writephy(tp, 0x11, 0x0a10);
5475 tg3_writephy(tp, 0x18, 0x00a0);
5476 tg3_writephy(tp, 0x16, 0x41ff);
5479 tg3_writephy(tp, 0x13, 0x0400);
5481 tg3_writephy(tp, 0x13, 0x0000);
5483 tg3_writephy(tp, 0x11, 0x0a50);
5485 tg3_writephy(tp, 0x11, 0x0a10);
5495 tg3_writephy(tp, 0x10, 0x8011);
5895 tg3_writephy(tp, MII_ADVERTISE, newadv);
5897 tg3_writephy(tp, MII_BMCR, bmcr);
5928 tg3_writephy(tp, MII_ADVERTISE, adv);
5929 tg3_writephy(tp, MII_BMCR, bmcr |
5935 tg3_writephy(tp, MII_BMCR, new_bmcr);
6020 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6024 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6037 tg3_writephy(tp, MII_BMCR, bmcr);
6047 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6055 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
8224 tg3_writephy(tp, MII_CTRL1000, val);
8228 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8233 tg3_writephy(tp, MII_BMCR, bmcr);
8243 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8274 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10701 tg3_writephy(tp, MII_TG3_TEST1,
11810 tg3_writephy(tp, MII_TG3_TEST1,
12418 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
15610 tg3_writephy(tp, MII_BMCR,