Lines Matching defs:val
470 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472 writel(val, tp->regs + off);
480 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482 writel(val, tp->aperegs + off);
490 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
500 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502 writel(val, tp->regs + off);
509 u32 val;
513 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 return val;
518 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
524 TG3_64BIT_REG_LOW, val);
529 TG3_64BIT_REG_LOW, val);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
542 (val == 0x1)) {
551 u32 val;
555 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 return val;
565 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
569 tp->write32(tp, off, val);
572 tg3_write32(tp, off, val);
584 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586 tp->write32_mbox(tp, off, val);
593 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 writel(val, mbox);
598 writel(val, mbox);
609 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611 writel(val, tp->regs + off + GRCMBOX_BASE);
614 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
615 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
616 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
617 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
620 #define tw32(reg, val) tp->write32(tp, reg, val)
621 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
622 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
625 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
642 tw32_f(TG3PCI_MEM_WIN_DATA, val);
650 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
656 *val = 0;
663 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
669 *val = tr32(TG3PCI_MEM_WIN_DATA);
900 u32 val = tg3_ape_read32(tp, msgoff + i);
901 memcpy(data, &val, sizeof(u32));
1118 u32 *val)
1132 *val = 0x0;
1157 *val = frame_val & MI_COM_DATA_MASK;
1171 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1173 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1177 u32 val)
1199 frame_val |= (val & MI_COM_DATA_MASK);
1230 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1232 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1235 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1258 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1275 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1281 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1287 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1292 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1303 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1311 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1326 u32 val;
1329 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1335 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1337 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1340 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1345 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1348 reg | val | MII_TG3_MISC_SHDW_WREN);
1385 u32 val;
1389 if (__tg3_readphy(tp, mii_id, reg, &val))
1390 val = -EIO;
1394 return val;
1397 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1404 if (__tg3_writephy(tp, mii_id, reg, val))
1414 u32 val;
1421 val = MAC_PHYCFG2_50610_LED_MODES;
1424 val = MAC_PHYCFG2_AC131_LED_MODES;
1427 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1430 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1437 tw32(MAC_PHYCFG2, val);
1439 val = tr32(MAC_PHYCFG1);
1440 val &= ~(MAC_PHYCFG1_RGMII_INT |
1442 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1443 tw32(MAC_PHYCFG1, val);
1449 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1456 tw32(MAC_PHYCFG2, val);
1458 val = tr32(MAC_PHYCFG1);
1459 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1463 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1465 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1467 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1469 tw32(MAC_PHYCFG1, val);
1471 val = tr32(MAC_EXT_RGMII_MODE);
1472 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1481 val |= MAC_RGMII_MODE_RX_INT_B |
1486 val |= MAC_RGMII_MODE_TX_ENABLE |
1490 tw32(MAC_EXT_RGMII_MODE, val);
1616 u32 val;
1618 val = tr32(GRC_RX_CPU_EVENT);
1619 val |= GRC_RX_CPU_DRIVER_EVENT;
1620 tw32_f(GRC_RX_CPU_EVENT, val);
1660 u32 reg, val;
1662 val = 0;
1664 val = reg << 16;
1666 val |= (reg & 0xffff);
1667 *data++ = val;
1669 val = 0;
1671 val = reg << 16;
1673 val |= (reg & 0xffff);
1674 *data++ = val;
1676 val = 0;
1679 val = reg << 16;
1681 val |= (reg & 0xffff);
1683 *data++ = val;
1686 val = reg << 16;
1688 val = 0;
1689 *data++ = val;
1809 u32 val;
1834 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1835 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2171 u32 val;
2186 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2190 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2192 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2293 u32 val;
2298 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2301 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2343 u32 val;
2352 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2356 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2357 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2365 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2368 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2370 dest->eee_enabled = !!val;
2371 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2374 val = tr32(TG3_CPMU_EEE_MODE);
2375 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2383 u32 val;
2416 val = tr32(TG3_CPMU_EEE_MODE);
2417 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2423 u32 val;
2430 val = MII_TG3_DSP_TAP26_ALNOKO |
2432 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2436 val = tr32(TG3_CPMU_EEE_MODE);
2437 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2630 u32 val, cpmuctrl;
2634 val = tr32(GRC_MISC_CFG);
2635 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2638 err = tg3_readphy(tp, MII_BMSR, &val);
2639 err |= tg3_readphy(tp, MII_BMSR, &val);
2671 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2672 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2679 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2680 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2682 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2684 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2741 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2744 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2751 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2753 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
3057 u32 val;
3077 val = tr32(GRC_MISC_CFG);
3078 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3106 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3109 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3120 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3121 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3122 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3123 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3184 u32 offset, u32 *val)
3218 *val = swab32(tmp);
3280 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3285 return tg3_nvram_read_using_eeprom(tp, offset, val);
3303 *val = tr32(NVRAM_RDDATA);
3313 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3318 *val = cpu_to_be32(v);
3326 u32 val;
3344 val = tr32(GRC_EEPROM_ADDR);
3345 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3347 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3349 tw32(GRC_EEPROM_ADDR, val |
3356 val = tr32(GRC_EEPROM_ADDR);
3358 if (val & EEPROM_ADDR_COMPLETE)
3362 if (!(val & EEPROM_ADDR_COMPLETE)) {
3637 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3639 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3827 u32 val;
3844 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3845 if (val & 0xff) {
4105 u32 val;
4107 val = tr32(GRC_VCPU_EXT_CTRL);
4108 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4111 u32 val;
4114 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4115 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4248 u32 val = tr32(0x7d00);
4250 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4251 tw32(0x7d00, val);
4275 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
4277 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4310 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4312 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4325 u32 val, new_adv;
4357 val = 0;
4360 val |= MDIO_AN_EEE_ADV_100TX;
4363 val |= MDIO_AN_EEE_ADV_1000T;
4366 val = 0;
4374 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4376 val = 0;
4384 if (val)
4385 val = MII_TG3_DSP_TAP26_ALNOKO |
4388 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4392 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4393 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4506 u32 val;
4508 err = tg3_readphy(tp, MII_BMCR, &val);
4512 if (!(val & BMCR_ANENABLE)) {
4519 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4542 if (val & BMCR_FULLDPLX)
4560 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4564 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4576 err = tg3_readphy(tp, MII_CTRL1000, &val);
4580 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4582 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4586 adv = tg3_decode_flowctrl_1000X(val);
4589 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4590 adv = mii_adv_to_ethtool_adv_x(val);
4691 u32 val;
4693 if (tg3_readphy(tp, MII_STAT1000, &val))
4696 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4740 u32 val;
4742 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4745 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4747 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4752 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4758 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4761 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4777 u32 bmsr, val;
4850 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4876 &val);
4877 if (!err && !(val & (1 << 10))) {
4880 val | (1 << 10));
4964 if (!tg3_readphy(tp, reg, &val) && (val & bit))
5527 u32 val = serdes_cfg;
5530 val |= 0xc010000;
5532 val |= 0x4010000;
5533 tw32_f(MAC_SERDES_CFG, val);
5604 u32 val = serdes_cfg;
5607 val |= 0xc010000;
5609 val |= 0x4010000;
5611 tw32_f(MAC_SERDES_CFG, val);
6065 u32 val;
6078 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6079 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6081 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6086 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6087 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6088 tw32(GRC_MISC_CFG, val);
6091 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6095 val |= tr32(MAC_TX_LENGTHS) &
6101 tw32(MAC_TX_LENGTHS, val |
6104 tw32(MAC_TX_LENGTHS, val |
6117 val = tr32(PCIE_PWR_MGMT_THRESH);
6119 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6122 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6123 tw32(PCIE_PWR_MGMT_THRESH, val);
7286 u32 val;
7293 val = tr32(HOSTCC_FLOW_ATTN);
7294 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
8193 u32 val, bmcr, mac_mode, ptest = 0;
8221 tg3_readphy(tp, MII_CTRL1000, &val);
8222 val |= CTL1000_AS_MASTER |
8224 tg3_writephy(tp, MII_CTRL1000, val);
8248 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8823 u32 val;
8842 val = tr32(ofs);
8843 val &= ~enable_bit;
8844 tw32_f(ofs, val);
8856 val = tr32(ofs);
8857 if ((val & enable_bit) == 0)
8952 u32 val;
8959 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8962 val |= PCISTATE_RETRY_SAME_DMA;
8965 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8968 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
9004 val = tr32(MSGINT_MODE);
9005 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
9012 u32 val;
9016 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9017 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9033 u32 val;
9037 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9039 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9044 val = tr32(TG3_CPMU_CLCK_ORIDE);
9045 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9058 u32 val;
9120 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9121 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9125 val = GRC_MISC_CFG_CORECLK_RESET;
9137 val |= (1 << 29);
9156 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9158 tw32(GRC_MISC_CFG, val);
9184 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9227 val = 0;
9229 val = tr32(MEMARB_MODE);
9230 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9254 val = tr32(0xc4);
9256 tw32(0xc4, val | (1 << 15));
9269 val = tp->mac_mode;
9272 val = tp->mac_mode;
9274 val = 0;
9276 tw32_f(MAC_MODE, val);
9287 val = tr32(0x7c00);
9289 tw32(0x7c00, val | (1 << 25));
9298 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9299 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9309 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9310 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9501 u32 val = ec->stats_block_coalesce_usecs;
9507 val = 0;
9509 tw32(HOSTCC_STAT_COAL_TICKS, val);
9673 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9690 val = min(nic_rep_thresh, host_rep_thresh);
9691 tw32(RCVBDI_STD_THRESH, val);
9703 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9704 tw32(RCVBDI_JUMBO_THRESH, val);
9847 u32 val = tp->rss_ind_tbl[i];
9850 val <<= 4;
9851 val |= tp->rss_ind_tbl[i];
9853 tw32(reg, val);
9869 u32 val, rdmac_mode;
9903 val = tr32(TG3_CPMU_CTRL);
9904 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9905 tw32(TG3_CPMU_CTRL, val);
9907 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9908 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9909 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9910 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9912 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9913 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9914 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9915 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9917 val = tr32(TG3_CPMU_HST_ACC);
9918 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9919 val |= CPMU_HST_ACC_MACCLK_6_25;
9920 tw32(TG3_CPMU_HST_ACC, val);
9924 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9925 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9927 tw32(PCIE_PWR_MGMT_THRESH, val);
9929 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9930 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9934 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9935 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9942 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9943 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9945 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9947 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9957 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9958 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9960 val = tr32(TG3_PCIE_TLDLPL_PORT +
9963 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9972 val = tr32(TG3_CPMU_PADRNG_CTL);
9973 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9974 tw32(TG3_CPMU_PADRNG_CTL, val);
9979 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9980 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9982 val = tr32(TG3_PCIE_TLDLPL_PORT +
9984 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9986 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9991 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9992 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9993 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9994 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
10010 val = tr32(TG3PCI_PCISTATE);
10011 val |= PCISTATE_RETRY_SAME_DMA;
10012 tw32(TG3PCI_PCISTATE, val);
10019 val = tr32(TG3PCI_PCISTATE);
10020 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
10023 tw32(TG3PCI_PCISTATE, val);
10028 val = tr32(TG3PCI_MSI_DATA);
10029 val |= (1 << 26) | (1 << 28) | (1 << 29);
10030 tw32(TG3PCI_MSI_DATA, val);
10043 val = tr32(TG3PCI_DMA_RW_CTRL) &
10046 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
10050 val |= DMA_RWCTRL_TAGGED_STAT_WA;
10051 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10074 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10080 val |= GRC_MODE_TIME_SYNC_ENABLE;
10082 tw32(GRC_MODE, tp->grc_mode | val);
10090 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
10091 tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
10095 val = tr32(GRC_MISC_CFG);
10096 val &= ~0xff;
10097 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10098 tw32(GRC_MISC_CFG, val);
10142 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10144 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10149 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10150 tw32(BUFMGR_MODE, val);
10207 val = TG3_RX_JMB_RING_SIZE(tp) <<
10210 val | BDINFO_FLAGS_USE_EXT_RECV);
10222 val = TG3_RX_STD_RING_SIZE(tp);
10223 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10224 val |= (TG3_RX_STD_DMA_SZ << 2);
10226 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10228 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10230 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10251 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10257 val |= tr32(MAC_TX_LENGTHS) &
10261 tw32(MAC_TX_LENGTHS, val);
10333 val = tr32(tgtreg);
10336 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10339 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10343 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10356 val = tr32(tgtreg);
10357 tw32(tgtreg, val |
10364 val = tr32(RCVLPC_STATS_ENABLE);
10365 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10366 tw32(RCVLPC_STATS_ENABLE, val);
10369 val = tr32(RCVLPC_STATS_ENABLE);
10370 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10371 tw32(RCVLPC_STATS_ENABLE, val);
10471 val = tr32(MSGINT_MODE);
10472 val |= MSGINT_MODE_ENABLE;
10474 val |= MSGINT_MODE_MULTIVEC_EN;
10476 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10477 tw32(MSGINT_MODE, val);
10485 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10499 val |= WDMAC_MODE_RX_ACCEL;
10505 val |= WDMAC_MODE_STATUS_TAG_FIX;
10508 val |= WDMAC_MODE_BURST_ALL_DATA;
10510 tw32_f(WDMAC_MODE, val);
10539 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10540 val |= tg3_lso_rd_dma_workaround_bit(tp);
10541 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10558 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10560 val |= RCVDBDI_MODE_LRG_RING_SZ;
10561 tw32(RCVDBDI_MODE, val);
10567 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10569 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10570 tw32(SNDBDI_MODE, val);
10600 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10601 tp->tx_mode &= ~val;
10602 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10652 val = tr32(MAC_SERDES_CFG);
10653 val &= 0xfffff000;
10654 val |= 0x880;
10655 tw32(MAC_SERDES_CFG, val);
10665 val = 1;
10667 val = 2;
10668 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10916 u32 val;
10918 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10919 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10920 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10946 u32 val = tr32(HOSTCC_FLOW_ATTN);
10947 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10948 if (val) {
10950 sp->rx_discards.low += val;
10951 if (sp->rx_discards.low < val)
11281 u32 val;
11295 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11296 tw32(MSGINT_MODE, val);
11341 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11342 tw32(MSGINT_MODE, val);
11634 u32 val = tr32(PCIE_TRANSACTION_CFG);
11637 val | PCIE_TRANS_CFG_1SHOT_MSI);
11795 static inline u64 get_stat64(tg3_stat64_t *val)
11797 return ((u64)val->high << 32) | ((u64)val->low);
11807 u32 val;
11809 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11811 val | MII_TG3_TEST1_CRC_EN);
11812 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11814 val = 0;
11816 tp->phy_crc_errors += val;
12024 __be32 val;
12056 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
12059 memcpy(data, ((char *)&val) + b_offset, b_count);
12068 ret = tg3_nvram_read_be32(tp, offset + i, &val);
12075 memcpy(pd + i, &val, 4);
12092 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12095 memcpy(pd, &val, b_count);
12831 u32 magic, val;
12840 if (tg3_nvram_read(tp, offset, &val))
12843 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12849 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
13084 u32 offset, read_mask, write_mask, val, save_val, read_val;
13266 val = tr32(offset);
13269 if (((val & read_mask) != read_val) || (val & write_mask))
13278 val = tr32(offset);
13281 if ((val & read_mask) != read_val)
13285 if ((val & write_mask) != write_mask)
13309 u32 val;
13312 tg3_read_mem(tp, offset + j, &val);
13313 if (val != test_pattern[i])
13416 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13459 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13460 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13472 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13473 th = (struct tcphdr *)&tx_data[val];
13511 val = tnapi->tx_prod;
13512 tnapi->tx_buffers[val].skb = skb;
13513 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13523 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13525 tnapi->tx_buffers[val].skb = NULL;
13563 val = data_off;
13608 for (i = data_off; i < rx_len; i++, val++) {
13609 if (*(rx_data + i) != (u8) (val & 0xff))
14311 u32 cursize, val, magic;
14331 if (tg3_nvram_read(tp, cursize, &val) != 0)
14334 if (val == magic)
14345 u32 val;
14347 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14351 if (val != TG3_EEPROM_MAGIC) {
14356 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14357 if (val != 0) {
14369 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14975 u32 val;
14977 if (tg3_nvram_read(tp, 0, &val))
14980 if (val != TG3_EEPROM_MAGIC &&
14981 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
15146 u32 val;
15160 val = tr32(VCPU_CFGSHDW);
15161 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15163 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15164 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15171 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15172 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15361 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15379 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15397 u32 val;
15404 val = tr32(OTP_STATUS);
15405 if (val & OTP_STATUS_CMD_DONE)
15410 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15725 u32 val;
15727 if (tg3_nvram_read(tp, offset, &val) ||
15728 (val & 0xfc000000) != 0x0c000000 ||
15729 tg3_nvram_read(tp, offset + 4, &val) ||
15730 val != 0)
15738 u32 val, offset, start, ver_offset;
15748 if (tg3_nvram_read(tp, offset, &val))
15751 if ((val & 0xfc000000) == 0x0c000000) {
15752 if (tg3_nvram_read(tp, offset + 4, &val))
15755 if (val == 0)
15790 u32 val, major, minor;
15793 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15796 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15798 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15804 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15810 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15813 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15836 if (tg3_nvram_read(tp, offset, &val))
15839 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15841 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15843 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15861 u32 val, offset, start;
15867 if (tg3_nvram_read(tp, offset, &val))
15870 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15884 tg3_nvram_read(tp, offset + 8, &val))
15887 offset += val - start;
15954 u32 val, val2;
15959 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15961 TG3_OTP_MAGIC0_VALID(val)) {
15962 u64 val64 = (u64) val << 32 | val2;
15979 u32 val;
15991 if (tg3_nvram_read(tp, 0, &val))
15994 if (val == TG3_EEPROM_MAGIC)
15996 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15997 tg3_read_sb_ver(tp, val);
15998 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
16173 u32 val;
16602 val = tr32(MEMARB_MODE);
16603 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16611 &val);
16612 tp->pci_fn = val & 0x7;
16617 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16618 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16619 val = tr32(TG3_CPMU_STATUS);
16622 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16624 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16789 val = tr32(GRC_MODE);
16792 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16798 val &= GRC_MODE_HOST_STACKUP;
16800 tw32(GRC_MODE, val | tp->grc_mode);
17027 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
17058 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17083 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17086 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17092 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17097 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17107 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17108 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17114 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17115 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17122 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17129 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17136 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17143 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17149 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17153 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17158 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17165 return val;
17216 u32 val;
17218 val = *(((u32 *)&test_desc) + i);
17221 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17232 u32 val;
17235 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17237 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17238 if ((val & 0xffff) == sram_dma_descs) {