Lines Matching defs:tw32_f
621 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
641 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
642 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
668 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
672 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1125 tw32_f(MAC_MI_MODE,
1140 tw32_f(MAC_MI_COM, frame_val);
1162 tw32_f(MAC_MI_MODE, tp->mi_mode);
1188 tw32_f(MAC_MI_MODE,
1202 tw32_f(MAC_MI_COM, frame_val);
1221 tw32_f(MAC_MI_MODE, tp->mi_mode);
1496 tw32_f(MAC_MI_MODE, tp->mi_mode);
1620 tw32_f(GRC_RX_CPU_EVENT, val);
1988 tw32_f(MAC_RX_MODE, tp->rx_mode);
1996 tw32_f(MAC_TX_MODE, tp->tx_mode);
2043 tw32_f(MAC_MODE, tp->mac_mode);
2635 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2684 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3078 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3123 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3159 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3531 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3568 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3604 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3620 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3767 tw32_f(cpu_base + CPU_PC, pc);
3774 tw32_f(cpu_base + CPU_PC, pc);
4177 tw32_f(MAC_MODE, mac_mode);
4180 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4730 tw32_f(MAC_STATUS,
4747 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4749 tw32_f(TG3_CPMU_EEE_CTRL,
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4765 tw32_f(TG3_CPMU_EEE_DBTMR1,
4769 tw32_f(TG3_CPMU_EEE_DBTMR2,
4786 tw32_f(MAC_MI_MODE,
5040 tw32_f(MAC_MI_MODE, tp->mi_mode);
5044 tw32_f(MAC_MODE, tp->mac_mode);
5051 tw32_f(MAC_EVENT, 0);
5053 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5062 tw32_f(MAC_STATUS,
5232 tw32_f(MAC_MODE, tp->mac_mode);
5261 tw32_f(MAC_MODE, tp->mac_mode);
5276 tw32_f(MAC_MODE, tp->mac_mode);
5362 tw32_f(MAC_MODE, tp->mac_mode);
5411 tw32_f(MAC_TX_AUTO_NEG, 0);
5414 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5434 tw32_f(MAC_MODE, tp->mac_mode);
5533 tw32_f(MAC_SERDES_CFG, val);
5536 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5566 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5567 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5569 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5611 tw32_f(MAC_SERDES_CFG, val);
5614 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5675 tw32_f(MAC_STATUS,
5696 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5699 tw32_f(MAC_MODE, tp->mac_mode);
5730 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5736 tw32_f(MAC_TX_AUTO_NEG, 0);
5740 tw32_f(MAC_MODE, tp->mac_mode);
5747 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5763 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5777 tw32_f(MAC_MODE, (tp->mac_mode |
5780 tw32_f(MAC_MODE, tp->mac_mode);
5849 tw32_f(MAC_MODE, tp->mac_mode);
5858 tw32_f(MAC_MODE, tp->mac_mode);
5899 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5991 tw32_f(MAC_MODE, tp->mac_mode);
5994 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
6150 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
7023 tw32_f(MAC_STATUS,
7205 tw32_f(HOSTCC_MODE, tp->coal_now);
8254 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8256 tw32_f(MAC_RX_MODE, tp->rx_mode);
8844 tw32_f(ofs, val);
8886 tw32_f(MAC_RX_MODE, tp->rx_mode);
8905 tw32_f(MAC_MODE, tp->mac_mode);
8909 tw32_f(MAC_TX_MODE, tp->tx_mode);
9276 tw32_f(MAC_MODE, val);
9806 tw32_f(MAC_RX_MODE, rx_mode);
10005 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
10423 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10436 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10467 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10481 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10510 tw32_f(WDMAC_MODE, val);
10529 tw32_f(RDMAC_MODE, rdmac_mode);
10605 tw32_f(MAC_TX_MODE, tp->tx_mode);
10634 tw32_f(MAC_RX_MODE, tp->rx_mode);
10641 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10644 tw32_f(MAC_RX_MODE, tp->rx_mode);
10668 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
11060 tw32_f(MAC_MODE,
11064 tw32_f(MAC_MODE, tp->mac_mode);
11307 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13515 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13542 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
14997 tw32_f(GRC_EEPROM_ADDR,
15005 tw32_f(GRC_LOCAL_CTRL,
16971 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
17205 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17210 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);