Lines Matching defs:tw32
620 #define tw32(reg, val) tp->write32(tp, reg, val)
1001 tw32(TG3PCI_MISC_HOST_CTRL,
1014 tw32(TG3PCI_MISC_HOST_CTRL,
1031 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1033 tw32(HOSTCC_MODE, tp->coal_now);
1078 tw32(HOSTCC_MODE, tp->coalesce_mode |
1437 tw32(MAC_PHYCFG2, val);
1443 tw32(MAC_PHYCFG1, val);
1456 tw32(MAC_PHYCFG2, val);
1469 tw32(MAC_PHYCFG1, val);
1490 tw32(MAC_EXT_RGMII_MODE, val);
2049 tw32(MAC_MI_STAT,
2053 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2057 tw32(MAC_TX_LENGTHS,
2062 tw32(MAC_TX_LENGTHS,
2402 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2417 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2437 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2662 tw32(TG3_CPMU_CTRL,
2674 tw32(TG3_CPMU_CTRL, cpmuctrl);
2803 tw32(TG3_CPMU_DRV_STATUS, status);
3069 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3070 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3136 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3143 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3169 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3179 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3195 tw32(GRC_EEPROM_ADDR,
3229 tw32(NVRAM_CMD, nvram_cmd);
3298 tw32(NVRAM_ADDR, offset);
3342 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3345 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3349 tw32(GRC_EEPROM_ADDR, val |
3423 tw32(NVRAM_ADDR, phy_addr);
3442 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3444 tw32(NVRAM_ADDR, phy_addr + j);
3481 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3500 tw32(NVRAM_ADDR, phy_addr);
3547 tw32(NVRAM_WRITE1, 0x406);
3550 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3561 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3587 tw32(cpu_base + CPU_STATE, 0xffffffff);
3588 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3603 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3619 tw32(cpu_base + CPU_STATE, 0xffffffff);
3639 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3663 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3728 tw32(cpu_base + CPU_STATE, 0xffffffff);
3729 tw32(cpu_base + CPU_MODE,
3766 tw32(cpu_base + CPU_STATE, 0xffffffff);
3772 tw32(cpu_base + CPU_STATE, 0xffffffff);
3773 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3956 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3957 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3960 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3961 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3990 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4035 tw32(TG3PCI_MISC_HOST_CTRL,
4108 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4165 tw32(MAC_LED_CTRL, tp->led_ctrl);
4251 tw32(0x7d00, val);
4350 tw32(TG3_CPMU_EEE_MODE,
4728 tw32(MAC_EVENT, 0);
5018 tw32(MAC_LED_CTRL, led_ctrl);
5230 tw32(MAC_TX_AUTO_NEG, 0);
5259 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5274 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5787 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5793 tw32(MAC_LED_CTRL, (tp->led_ctrl |
6088 tw32(GRC_MISC_CFG, val);
6101 tw32(MAC_TX_LENGTHS, val |
6104 tw32(MAC_TX_LENGTHS, val |
6109 tw32(HOSTCC_STAT_COAL_TICKS,
6112 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6123 tw32(PCIE_PWR_MGMT_THRESH, val);
6147 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6148 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6149 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6199 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6204 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6294 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6295 tw32(TG3_EAV_WATCHDOG0_MSB,
6299 tw32(TG3_EAV_REF_CLCK_CTL,
6302 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6303 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
7266 tw32(HOSTCC_MODE, tp->coalesce_mode |
8187 tw32(MAC_MODE, tp->mac_mode);
8278 tw32(MAC_MODE, mac_mode);
8927 tw32(FTQ_RESET, 0xffffffff);
8928 tw32(FTQ_RESET, 0x00000000);
9005 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
9017 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9023 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9038 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9045 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9082 tw32(GRC_FASTBOOT_PC, 0);
9121 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9133 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9136 tw32(GRC_MISC_CFG, (1 << 29));
9142 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9143 tw32(GRC_VCPU_EXT_CTRL,
9158 tw32(GRC_MISC_CFG, val);
9230 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9234 tw32(0x5000, 0x400);
9251 tw32(GRC_MODE, tp->grc_mode);
9256 tw32(0xc4, val | (1 << 15));
9264 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9289 tw32(0x7c00, val | (1 << 25));
9299 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9434 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9435 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9436 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9438 tw32(HOSTCC_TXCOL_TICKS, 0);
9439 tw32(HOSTCC_TXMAX_FRAMES, 0);
9440 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9446 tw32(reg, ec->tx_coalesce_usecs);
9448 tw32(reg, ec->tx_max_coalesced_frames);
9450 tw32(reg, ec->tx_max_coalesced_frames_irq);
9455 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9456 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9457 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9467 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9468 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9469 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9472 tw32(HOSTCC_RXCOL_TICKS, 0);
9473 tw32(HOSTCC_RXMAX_FRAMES, 0);
9474 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9481 tw32(reg, ec->rx_coalesce_usecs);
9483 tw32(reg, ec->rx_max_coalesced_frames);
9485 tw32(reg, ec->rx_max_coalesced_frames_irq);
9489 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9490 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9491 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9503 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9504 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9509 tw32(HOSTCC_STAT_COAL_TICKS, val);
9650 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9652 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9659 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9660 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9691 tw32(RCVBDI_STD_THRESH, val);
9694 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9704 tw32(RCVBDI_JUMBO_THRESH, val);
9707 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9737 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9738 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9739 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9740 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9784 tw32(MAC_HASH_REG_0, mc_filter[0]);
9785 tw32(MAC_HASH_REG_1, mc_filter[1]);
9786 tw32(MAC_HASH_REG_2, mc_filter[2]);
9787 tw32(MAC_HASH_REG_3, mc_filter[3]);
9853 tw32(reg, val);
9905 tw32(TG3_CPMU_CTRL, val);
9910 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9915 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9920 tw32(TG3_CPMU_HST_ACC, val);
9927 tw32(PCIE_PWR_MGMT_THRESH, val);
9930 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9932 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9935 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9943 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9946 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9949 tw32(GRC_MODE, grc_mode);
9958 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9962 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9965 tw32(GRC_MODE, grc_mode);
9974 tw32(TG3_CPMU_PADRNG_CTL, val);
9980 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9985 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9988 tw32(GRC_MODE, grc_mode);
9994 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
10012 tw32(TG3PCI_PCISTATE, val);
10023 tw32(TG3PCI_PCISTATE, val);
10030 tw32(TG3PCI_MSI_DATA, val);
10051 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10057 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10076 tw32(TG3_RX_PTP_CTL,
10082 tw32(GRC_MODE, tp->grc_mode | val);
10091 tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
10098 tw32(GRC_MISC_CFG, val);
10104 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10106 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10108 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10109 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10110 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10116 tw32(BUFMGR_MB_POOL_ADDR,
10118 tw32(BUFMGR_MB_POOL_SIZE,
10123 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10125 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10127 tw32(BUFMGR_MB_HIGH_WATER,
10130 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10132 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10134 tw32(BUFMGR_MB_HIGH_WATER,
10137 tw32(BUFMGR_DMA_LOW_WATER,
10139 tw32(BUFMGR_DMA_HIGH_WATER,
10150 tw32(BUFMGR_MODE, val);
10162 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10183 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10185 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10188 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10193 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10203 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10205 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10209 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10214 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10217 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10230 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10245 tw32(MAC_RX_MTU_SIZE,
10261 tw32(MAC_TX_LENGTHS, val);
10264 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10265 tw32(RCVLPC_CONFIG, 0x0181);
10343 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10357 tw32(tgtreg, val |
10366 tw32(RCVLPC_STATS_ENABLE, val);
10371 tw32(RCVLPC_STATS_ENABLE, val);
10373 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10375 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10376 tw32(SNDDATAI_STATSENAB, 0xffffff);
10377 tw32(SNDDATAI_STATSCTRL,
10382 tw32(HOSTCC_MODE, 0);
10396 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10398 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10400 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10402 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10413 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10415 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10416 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10418 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10477 tw32(MSGINT_MODE, val);
10541 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10546 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10548 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10551 tw32(SNDDATAC_MODE,
10554 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10556 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10557 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10561 tw32(RCVDBDI_MODE, val);
10562 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10566 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10570 tw32(SNDBDI_MODE, val);
10571 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10616 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10637 tw32(MAC_LED_CTRL, tp->led_ctrl);
10639 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10655 tw32(MAC_SERDES_CFG, val);
10658 tw32(MAC_SERDES_CFG, 0x616000);
10681 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10684 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10711 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10712 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10713 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10714 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10724 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10727 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10730 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10733 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10736 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10739 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10742 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10745 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10748 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10751 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10754 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10757 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10760 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10762 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10794 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10920 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10949 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
11008 tw32(GRC_LOCAL_CTRL,
11011 tw32(HOSTCC_MODE, tp->coalesce_mode |
11296 tw32(MSGINT_MODE, val);
11342 tw32(MSGINT_MODE, val);
11540 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11636 tw32(PCIE_TRANSACTION_CFG,
12040 tw32(TG3_CPMU_CTRL, cpmu_val &
12104 tw32(TG3_CPMU_CTRL, cpmu_val);
12793 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12803 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12808 tw32(MAC_LED_CTRL, tp->led_ctrl);
13264 tw32(offset, 0);
13276 tw32(offset, read_mask | write_mask);
13288 tw32(offset, save_val);
13297 tw32(offset, save_val);
13447 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13664 tw32(i, 0x0);
13905 tw32(TG3_RX_PTP_CTL,
14385 tw32(NVRAM_CFG1, nvcfg1);
14491 tw32(NVRAM_CFG1, nvcfg1);
14567 tw32(NVRAM_CFG1, nvcfg1);
14685 tw32(NVRAM_CFG1, nvcfg1);
14758 tw32(NVRAM_CFG1, nvcfg1);
14875 tw32(NVRAM_CFG1, nvcfg1);
15399 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15400 tw32(OTP_CTRL, cmd);
15421 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15426 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15433 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
16603 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16800 tw32(GRC_MODE, val | tp->grc_mode);
16805 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16808 tw32(TG3PCI_REG_BASE_ADDR, 0);
17177 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17178 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17179 tw32(RDMAC_STATUS, 0);
17180 tw32(WDMAC_STATUS, 0);
17182 tw32(BUFMGR_MODE, 0);
17183 tw32(FTQ_RESET, 0);
17226 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17228 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17344 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17356 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17390 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17421 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17875 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);