Lines Matching defs:tr32
623 #define tr32(reg) tp->read32(tp, reg)
669 *val = tr32(TG3PCI_MEM_WIN_DATA);
1090 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1145 frame_val = tr32(MAC_MI_COM);
1149 frame_val = tr32(MAC_MI_COM);
1207 frame_val = tr32(MAC_MI_COM);
1210 frame_val = tr32(MAC_MI_COM);
1439 val = tr32(MAC_PHYCFG1);
1458 val = tr32(MAC_PHYCFG1);
1471 val = tr32(MAC_EXT_RGMII_MODE);
1516 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1518 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1618 val = tr32(GRC_RX_CPU_EVENT);
1648 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1822 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
2374 val = tr32(TG3_CPMU_EEE_MODE);
2378 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2416 val = tr32(TG3_CPMU_EEE_MODE);
2436 val = tr32(TG3_CPMU_EEE_MODE);
2634 val = tr32(GRC_MISC_CFG);
2660 cpmuctrl = tr32(TG3_CPMU_CTRL);
2679 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2793 status = tr32(TG3_CPMU_DRV_STATUS);
3064 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3065 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3077 val = tr32(GRC_MISC_CFG);
3120 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3138 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3167 u32 nvaccess = tr32(NVRAM_ACCESS);
3177 u32 nvaccess = tr32(NVRAM_ACCESS);
3192 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3203 tmp = tr32(GRC_EEPROM_ADDR);
3212 tmp = tr32(GRC_EEPROM_DATA);
3232 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3303 *val = tr32(NVRAM_RDDATA);
3344 val = tr32(GRC_EEPROM_ADDR);
3356 val = tr32(GRC_EEPROM_ADDR);
3549 grc_mode = tr32(GRC_MODE);
3560 grc_mode = tr32(GRC_MODE);
3589 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3637 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3730 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3770 if (tr32(cpu_base + CPU_PC) == pc)
3813 tr32(RX_CPU_BASE + CPU_PC),
3833 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3936 __func__, tr32(cpu_base + CPU_PC),
4034 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4107 val = tr32(GRC_VCPU_EXT_CTRL);
4248 u32 val = tr32(0x7d00);
4351 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
5006 u32 led_ctrl = tr32(MAC_LED_CTRL);
5171 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5172 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5450 u32 mac_status = tr32(MAC_STATUS);
5514 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5519 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5522 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5575 sg_dig_status = tr32(SG_DIG_STATUS);
5576 mac_status = tr32(MAC_STATUS);
5620 mac_status = tr32(MAC_STATUS);
5679 if ((tr32(MAC_STATUS) &
5685 mac_status = tr32(MAC_STATUS);
5723 mac_status = tr32(MAC_STATUS);
5751 mac_status = tr32(MAC_STATUS);
5766 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5772 mac_status = tr32(MAC_STATUS);
5871 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5940 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
6078 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6086 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6095 val |= tr32(MAC_TX_LENGTHS) &
6117 val = tr32(PCIE_PWR_MGMT_THRESH);
6135 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6137 stamp |= (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6145 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6271 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6384 *dst++ = tr32(off + i);
6457 regs[i / sizeof(u32)] = tr32(i);
6559 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6560 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6868 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6869 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
7293 val = tr32(HOSTCC_FLOW_ATTN);
7299 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7304 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7521 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7570 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7616 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
8842 val = tr32(ofs);
8856 val = tr32(ofs);
8913 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8919 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
9004 val = tr32(MSGINT_MODE);
9016 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9037 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9044 val = tr32(TG3_CPMU_CLCK_ORIDE);
9120 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9131 tr32(TG3_PCIE_PHY_TSTCTL) ==
9142 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9144 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9229 val = tr32(MEMARB_MODE);
9254 val = tr32(0xc4);
9287 val = tr32(0x7c00);
9298 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9389 addr0_high = tr32(MAC_ADDR_0_HIGH);
9390 addr0_low = tr32(MAC_ADDR_0_LOW);
9391 addr1_high = tr32(MAC_ADDR_1_HIGH);
9392 addr1_low = tr32(MAC_ADDR_1_LOW);
9903 val = tr32(TG3_CPMU_CTRL);
9907 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9912 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9917 val = tr32(TG3_CPMU_HST_ACC);
9924 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9929 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9934 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9939 u32 grc_mode = tr32(GRC_MODE);
9945 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9954 u32 grc_mode = tr32(GRC_MODE);
9960 val = tr32(TG3_PCIE_TLDLPL_PORT +
9972 val = tr32(TG3_CPMU_PADRNG_CTL);
9976 grc_mode = tr32(GRC_MODE);
9982 val = tr32(TG3_PCIE_TLDLPL_PORT +
9991 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
10010 val = tr32(TG3PCI_PCISTATE);
10019 val = tr32(TG3PCI_PCISTATE);
10028 val = tr32(TG3PCI_MSI_DATA);
10043 val = tr32(TG3PCI_DMA_RW_CTRL) &
10090 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
10095 val = tr32(GRC_MISC_CFG);
10152 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10162 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10257 val |= tr32(MAC_TX_LENGTHS) &
10290 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10319 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10333 val = tr32(tgtreg);
10356 val = tr32(tgtreg);
10364 val = tr32(RCVLPC_STATS_ENABLE);
10369 val = tr32(RCVLPC_STATS_ENABLE);
10384 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10460 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10471 val = tr32(MSGINT_MODE);
10497 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10535 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10539 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10602 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10652 val = tr32(MAC_SERDES_CFG);
10680 tmp = tr32(SERDES_RX_CTRL);
10887 do { u32 __val = tr32(REG); \
10918 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10946 u32 val = tr32(HOSTCC_FLOW_ATTN);
10999 tr32(HOSTCC_MODE);
11015 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11034 mac_stat = tr32(MAC_STATUS);
11046 u32 mac_stat = tr32(MAC_STATUS);
11073 u32 cpmu = tr32(TG3_CPMU_STATUS);
11295 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11314 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11341 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11535 u32 msi_mode = tr32(MSGINT_MODE);
11634 u32 val = tr32(PCIE_TRANSACTION_CFG);
12037 cpmu_val = tr32(TG3_CPMU_CTRL);
13256 save_val = tr32(offset);
13266 val = tr32(offset);
13278 val = tr32(offset);
13694 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
14380 nvcfg1 = tr32(NVRAM_CFG1);
14458 nvcfg1 = tr32(NVRAM_CFG1);
14499 nvcfg1 = tr32(NVRAM_CFG1);
14555 nvcfg1 = tr32(NVRAM_CFG1);
14593 nvcfg1 = tr32(NVRAM_CFG1);
14633 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14675 nvcfg1 = tr32(NVRAM_CFG1);
14748 nvcfg1 = tr32(NVRAM_CFG1);
14826 nvcfg1 = tr32(NVRAM_CFG1);
14846 nv_status = tr32(NVRAM_AUTOSENSE_STATUS);
15006 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
15156 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15160 val = tr32(VCPU_CFGSHDW);
15404 val = tr32(OTP_STATUS);
15431 thalf_otp = tr32(OTP_READ_DATA);
15438 bhalf_otp = tr32(OTP_READ_DATA);
16150 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16602 val = tr32(MEMARB_MODE);
16619 val = tr32(TG3_CPMU_STATUS);
16697 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16789 val = tr32(GRC_MODE);
16842 grc_misc_cfg = tr32(GRC_MISC_CFG);
16944 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16968 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
17007 hi = tr32(MAC_ADDR_0_HIGH);
17008 lo = tr32(MAC_ADDR_0_LOW);
17235 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17237 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17289 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17524 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17529 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17813 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17872 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17873 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {