Lines Matching defs:set
1316 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1319 set |= MII_TG3_AUXCTL_MISC_WREN;
1321 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
3681 * the main header, the length field is unused and set to 0xffffffff.
3811 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3874 * here is unused and set to 0xffffffff.
3935 "%s fails to set CPU PC, is %08x should be %08x\n",
5003 * in RGMII mode, the Led Control Register must be set up.
5916 * to be set on write.
7176 /* run RX thread, within the bounds set by NAPI.
8400 /* Initialize invariants of the rings, we only set this
8683 * set on vector zero. This is the true hw prodring.
8740 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set.
9999 * other revision. But do not set this on PCI Express
10439 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10442 * whether used as inputs or outputs, are set by boot code after
10651 /* only if the signal pre-emphasis bit is not set */
14487 /* For eeprom, set pagesize to maximum eeprom size */
15318 /* serdes signal pre-emphasis in register 0x590 set by */
15319 /* bootcode if bit 18 is set */
15538 /* Do nothing, phy ID already set up in
16042 /* 5704 can be configured in single-port mode, set peer to
16179 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16637 * When the flag is set, it means that GPIO1 is used for eeprom
16899 /* The led_ctrl is set during tg3_phy_probe, here we might
17331 /* On 5700/5701 chips, we need to set this bit.
18194 * set up identically to what it was at cold boot.