Lines Matching defs:off
470 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472 writel(val, tp->regs + off);
475 static u32 tg3_read32(struct tg3 *tp, u32 off)
477 return readl(tp->regs + off);
480 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482 writel(val, tp->aperegs + off);
485 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487 return readl(tp->aperegs + off);
490 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
500 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502 writel(val, tp->regs + off);
503 readl(tp->regs + off);
506 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
518 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
522 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
527 if (off == TG3_RX_STD_PROD_IDX_REG) {
534 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
541 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
548 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
565 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
569 tp->write32(tp, off, val);
572 tg3_write32(tp, off, val);
575 tp->read32(tp, off);
584 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586 tp->write32_mbox(tp, off, val);
590 tp->read32_mbox(tp, off);
593 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
595 void __iomem *mbox = tp->regs + off;
604 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606 return readl(tp->regs + off + GRCMBOX_BASE);
609 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611 writel(val, tp->regs + off + GRCMBOX_BASE);
625 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
635 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
641 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
650 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
662 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
668 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
709 int i, off;
746 off = 4 * locknum;
748 tg3_ape_write32(tp, req + off, bit);
752 status = tg3_ape_read32(tp, gnt + off);
763 tg3_ape_write32(tp, gnt + off, bit);
1886 "on" : "off",
1888 "on" : "off");
4604 /* Turn off tap power management. */
6378 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6382 dst = (u32 *)((u8 *)dst + off);
6384 *dst++ = tr32(off + i);
10802 u32 off, len = TG3_OCIR_LEN;
10805 for (i = 0, off = 0; i < TG3_SD_NUM_RECS; i++, ocir++, off += len) {
10806 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
11291 * Turn off MSI one shot mode. Otherwise this test has no
11361 /* Turn off SERR reporting in case MSI terminates with Master
12790 return 1; /* cycle on/off once per second */
15364 u32 val2, off = offset * 8;
15370 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
16177 /* Force memory write invalidate off. If we leave it on,
16181 * workaround but turns MWI off all the times so never uses
16687 /* Turn off the debug UART. */
17771 * is off by default, but can be enabled using ethtool.