Lines Matching defs:err
848 int err;
879 err = tg3_ape_event_lock(tp, 1000);
880 if (err)
881 return err;
912 int err;
924 err = tg3_ape_event_lock(tp, 20000);
925 if (err)
926 return err;
1237 int err;
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1240 if (err)
1243 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1244 if (err)
1247 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1249 if (err)
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1255 return err;
1260 int err;
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1263 if (err)
1266 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1267 if (err)
1270 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1272 if (err)
1275 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1278 return err;
1283 int err;
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1286 if (!err)
1287 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1289 return err;
1294 int err;
1296 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1297 if (!err)
1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1300 return err;
1305 int err;
1307 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1310 if (!err)
1311 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1313 return err;
1327 int err;
1329 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1331 if (err)
1332 return err;
1339 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1342 return err;
1354 int limit, err;
1360 err = tg3_writephy(tp, MII_BMCR, phy_control);
1361 if (err != 0)
1366 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1367 if (err != 0)
2170 int err;
2178 err = tg3_phy_auxctl_write(tp,
2185 err = tg3_phy_auxctl_read(tp,
2187 if (err)
2188 return err;
2191 err = tg3_phy_auxctl_write(tp,
2195 return err;
2547 int retries, do_phy_reset, err;
2553 err = tg3_bmcr_reset(tp);
2554 if (err)
2555 return err;
2577 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2578 if (err)
2579 return err;
2584 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2585 if (!err)
2589 err = tg3_phy_reset_chanpat(tp);
2590 if (err)
2591 return err;
2602 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2603 if (err)
2604 return err;
2631 int err;
2638 err = tg3_readphy(tp, MII_BMSR, &val);
2639 err |= tg3_readphy(tp, MII_BMSR, &val);
2640 if (err != 0)
2651 err = tg3_phy_reset_5703_4_5(tp);
2652 if (err)
2653 return err;
2666 err = tg3_bmcr_reset(tp);
2667 if (err)
2668 return err;
2740 err = tg3_phy_auxctl_read(tp,
2742 if (!err)
3699 int err, i;
3720 err = tg3_halt_cpu(tp, cpu_base);
3723 if (err)
3754 err = 0;
3757 return err;
3785 int err;
3795 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3798 if (err)
3799 return err;
3801 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3804 if (err)
3805 return err;
3808 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3810 if (err) {
3900 int err;
3924 err = tg3_load_firmware_cpu(tp, cpu_base,
3927 if (err)
3928 return err;
3931 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3933 if (err) {
4005 int err;
4009 err = pci_set_power_state(tp->pdev, PCI_D0);
4010 if (!err) {
4017 return err;
4253 int err;
4255 err = tg3_nvram_lock(tp);
4257 if (!err)
4324 int err = 0;
4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4332 if (err)
4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4343 if (err)
4353 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4354 if (!err) {
4374 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4375 if (err)
4398 if (!err)
4399 err = err2;
4403 return err;
4505 int err;
4508 err = tg3_readphy(tp, MII_BMCR, &val);
4509 if (err)
4517 err = -EIO;
4549 err = 0;
4560 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4561 if (err)
4576 err = tg3_readphy(tp, MII_CTRL1000, &val);
4577 if (err)
4582 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4583 if (err)
4597 return err;
4602 int err;
4606 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4608 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4609 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4610 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4612 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4616 return err;
4781 int i, err;
4815 err = tg3_init_5401phy_dsp(tp);
4816 if (err)
4817 return err;
4833 err = tg3_phy_reset(tp);
4834 if (!err)
4835 err = tg3_init_5401phy_dsp(tp);
4836 if (err)
4837 return err;
4874 err = tg3_phy_auxctl_read(tp,
4877 if (!err && !(val & (1 << 10))) {
5811 int err = 0;
5868 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5869 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5877 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5885 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5903 return err;
5924 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5937 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5938 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5963 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5964 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
6000 return err;
6066 int err;
6069 err = tg3_setup_fiber_phy(tp, force_reset);
6071 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6073 err = tg3_setup_copper_phy(tp, force_reset);
6126 return err;
7041 int i, err = 0;
7069 err = -ENOSPC;
7127 err = -ENOSPC;
7159 return err;
7185 int i, err = 0;
7191 err |= tg3_rx_prodring_xfer(tp, dpr,
7204 if (err)
8874 int i, err;
8881 err = -ENODEV;
8889 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8890 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8891 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8892 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8893 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8894 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8896 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8897 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8898 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8899 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8900 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8901 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8902 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8920 err |= -ENODEV;
8923 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8924 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8925 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8930 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8931 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8940 return err;
9060 int i, err;
9247 err = tg3_poll_fw(tp);
9248 if (err)
9249 return err;
9338 int err, i;
9345 err = tg3_chip_reset(tp);
9368 return err;
9375 int err = 0;
9404 return err;
9870 int i, err, limit;
9896 err = tg3_chip_reset(tp);
9897 if (err)
9898 return err;
10038 err = tg3_init_rings(tp);
10039 if (err)
10040 return err;
10574 err = tg3_load_5701_a0_firmware_fix(tp);
10575 if (err)
10576 return err;
10587 err = tg3_load_tso_firmware(tp);
10588 if (err)
10589 return err;
10691 err = tg3_setup_phy(tp, false);
10692 if (err)
10693 return err;
11165 int err;
11167 err = tg3_init_hw(tp, reset_phy);
11168 if (err) {
11179 return err;
11185 int err;
11214 err = tg3_init_hw(tp, true);
11215 if (err) {
11280 int err, i, intr_ok = 0;
11299 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11301 if (err)
11302 return err;
11333 err = tg3_request_irq(tp, 0);
11335 if (err)
11336 return err;
11355 int err;
11368 err = tg3_test_interrupt(tp);
11372 if (!err)
11376 if (err != -EIO)
11377 return err;
11391 err = tg3_request_irq(tp, 0);
11392 if (err)
11393 return err;
11401 err = tg3_init_hw(tp, true);
11405 if (err)
11408 return err;
11572 int i, err;
11585 err = tg3_alloc_consistent(tp);
11586 if (err)
11594 err = tg3_request_irq(tp, i);
11595 if (err) {
11610 err = tg3_init_hw(tp, reset_phy);
11611 if (err) {
11618 if (err)
11622 err = tg3_test_msi(tp);
11624 if (err) {
11680 return err;
11721 int err;
11730 err = tg3_request_firmware(tp);
11732 if (err) {
11740 if (err)
11741 return err;
11742 } else if (err) {
11753 err = tg3_power_up(tp);
11754 if (err)
11755 return err;
11764 err = tg3_start(tp,
11767 if (err) {
11772 return err;
12458 int i, irq_sync = 0, err = 0;
12497 err = tg3_restart_hw(tp, reset_phy);
12498 if (!err)
12504 if (irq_sync && !err)
12507 return err;
12530 int err = 0;
12607 err = tg3_restart_hw(tp, reset_phy);
12608 if (!err)
12617 return err;
12901 int i, j, k, err = 0, size;
12948 err = -EIO;
12950 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12951 if (err)
12976 err = 0;
12980 err = -EIO;
13014 err = -EIO;
13023 err = 0;
13027 err = -EIO;
13045 err = pci_vpd_check_csum(buf, len);
13047 if (err == 1)
13048 err = 0;
13051 return err;
13364 int err = 0;
13382 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13383 if (err)
13387 return err;
13421 int num_pkts, tx_len, rx_len, i, err;
13436 err = -EIO;
13614 err = 0;
13618 return err;
13631 int err = -EIO;
13649 err = tg3_reset_hw(tp, true);
13650 if (err) {
13735 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13741 return err;
13770 int err, err2 = 0, irq_sync = 0;
13780 err = tg3_nvram_lock(tp);
13784 if (!err)
13982 int err;
14007 err = __tg3_readphy(tp, data->phy_id & 0x1f,
14013 return err;
14024 err = __tg3_writephy(tp, data->phy_id & 0x1f,
14028 return err;
14248 int err;
14278 err = tg3_restart_hw(tp, reset_phy);
14280 if (!err)
14285 if (!err)
14288 return err;
15363 int i, err;
15366 err = tg3_nvram_lock(tp);
15367 if (err)
15368 return err;
15476 int err;
15511 err = 0;
15520 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15521 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15530 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15600 err = tg3_phy_reset(tp);
15601 if (err)
15602 return err;
15617 err = tg3_init_5401phy_dsp(tp);
15618 if (err)
15619 return err;
15621 err = tg3_init_5401phy_dsp(tp);
15624 return err;
16175 int err;
16784 err = tg3_mdio_init(tp);
16785 if (err)
16786 return err;
16871 err = tg3_phy_probe(tp);
16872 if (err) {
16873 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16947 return err;
16954 int err;
16960 err = ssb_gige_get_macaddr(tp->pdev, addr);
16961 if (!err && is_valid_ether_addr(addr))
17368 "%s: Buffer write failed. err = %d\n",
17377 "err = %d\n", __func__, ret);
17590 int i, err;
17597 err = pci_enable_device(pdev);
17598 if (err) {
17600 return err;
17603 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17604 if (err) {
17613 err = -ENOMEM;
17674 err = -ENOMEM;
17698 err = -ENOMEM;
17711 err = tg3_get_invariants(tp, ent);
17712 if (err) {
17736 err = dma_set_mask(&pdev->dev, dma_mask);
17737 if (!err) {
17739 err = dma_set_coherent_mask(&pdev->dev,
17741 if (err < 0) {
17748 if (err || dma_mask == DMA_BIT_MASK(32)) {
17749 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
17750 if (err) {
17818 err = tg3_get_device_address(tp, addr);
17819 if (err) {
17880 err = tg3_test_dma(tp);
17881 if (err) {
17899 err = register_netdev(dev);
17900 if (err) {
17972 return err;
18013 int err = 0;
18037 err = tg3_power_down_prepare(tp);
18038 if (err) {
18062 return err;
18069 int err = 0;
18083 err = tg3_restart_hw(tp,
18085 if (err)
18095 if (!err)
18100 return err;
18141 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18177 err = PCI_ERS_RESULT_DISCONNECT;
18184 return err;
18201 int err;
18220 err = tg3_power_up(tp);
18221 if (err)
18247 int err;
18257 err = tg3_restart_hw(tp, true);
18258 if (err) {