Lines Matching refs:val
266 u32 val;
270 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
272 return val;
276 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
282 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
287 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
289 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
299 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
308 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
312 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
313 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
319 BNX2_WR(bp, BNX2_CTX_DATA, val);
486 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
521 *val = 0x0;
525 *val = val1;
543 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
558 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
1050 u32 val;
1052 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1053 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1055 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1108 u32 val, speed;
1113 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1121 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1137 if (val & MII_BNX2_GP_TOP_AN_FD)
1147 u32 val;
1150 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1151 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1165 if (val & BCM5708S_1000X_STAT1_FD)
1289 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1291 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1292 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1293 val |= 0x02 << 8;
1296 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
1298 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1317 u32 val;
1326 val = BNX2_RD(bp, BNX2_EMAC_MODE);
1328 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1336 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1341 val |= BNX2_EMAC_MODE_PORT_MII;
1344 val |= BNX2_EMAC_MODE_25G_MODE;
1347 val |= BNX2_EMAC_MODE_PORT_GMII;
1352 val |= BNX2_EMAC_MODE_PORT_GMII;
1357 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1358 BNX2_WR(bp, BNX2_EMAC_MODE, val);
1368 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
1369 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1372 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1373 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
1464 u32 val;
1468 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1469 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1470 val |= MII_BNX2_SD_MISC1_FORCE |
1472 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1508 u32 val;
1512 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1513 val &= ~MII_BNX2_SD_MISC1_FORCE;
1514 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1540 u32 val;
1543 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1545 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1547 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1573 u32 val, an_dbg;
1579 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
1585 if ((val & BNX2_EMAC_STATUS_LINK) &&
2182 u32 val;
2200 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2201 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2202 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2203 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2206 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2208 val |= BCM5708S_UP1_2G5;
2210 val &= ~BCM5708S_UP1_2G5;
2211 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2214 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2215 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2216 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2220 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2222 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2232 u32 val;
2243 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2244 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2245 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2247 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2248 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2249 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2252 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2253 val |= BCM5708S_UP1_2G5;
2254 bnx2_write_phy(bp, BCM5708S_UP1, val);
2263 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2264 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2265 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2269 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2272 if (val) {
2279 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2299 u32 val;
2303 bnx2_read_phy(bp, 0x18, &val);
2304 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2307 bnx2_read_phy(bp, 0x1c, &val);
2308 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2311 u32 val;
2314 bnx2_read_phy(bp, 0x18, &val);
2315 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2318 bnx2_read_phy(bp, 0x1c, &val);
2319 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2328 u32 val;
2347 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2348 val &= ~(1 << 8);
2349 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2355 bnx2_read_phy(bp, 0x18, &val);
2356 bnx2_write_phy(bp, 0x18, val | 0x4000);
2358 bnx2_read_phy(bp, 0x10, &val);
2359 bnx2_write_phy(bp, 0x10, val | 0x1);
2363 bnx2_read_phy(bp, 0x18, &val);
2364 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2366 bnx2_read_phy(bp, 0x10, &val);
2367 bnx2_write_phy(bp, 0x10, val & ~0x1);
2372 bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);
2373 val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED;
2377 val |= AUX_CTL_MISC_CTL_AUTOMDIX;
2379 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
2389 u32 val;
2406 bnx2_read_phy(bp, MII_PHYSID1, &val);
2407 bp->phy_id = val << 16;
2408 bnx2_read_phy(bp, MII_PHYSID2, &val);
2409 bp->phy_id |= val & 0xffff;
2522 u32 val;
2537 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2539 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2546 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2559 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2569 u32 val;
2571 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2572 val |= (BNX2_PAGE_BITS - 8) << 16;
2573 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
2575 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
2576 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2580 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2600 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2601 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2605 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2661 u32 val;
2673 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2674 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2678 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2680 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2683 if (!(val & (1 << 9))) {
2684 good_mbuf[good_mbuf_cnt] = (u16) val;
2688 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2696 val = good_mbuf[good_mbuf_cnt];
2697 val = (val << 9) | val | 1;
2699 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2708 u32 val;
2710 val = (mac_addr[0] << 8) | mac_addr[1];
2712 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2714 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2717 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
3777 u32 val, cmd, addr;
3798 val = (i / 8) | cmd;
3799 BNX2_WR(bp, addr, val);
3814 val = (loc / 2) | cmd;
3815 BNX2_WR(bp, addr, val);
3837 u32 val;
3840 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3841 val |= cpu_reg->mode_value_halt;
3842 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3890 val = be32_to_cpu(fw_entry->start_addr);
3891 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3894 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3895 val &= ~cpu_reg->mode_value_halt;
3897 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3932 u32 val, wol_msg;
3959 val = BNX2_RD(bp, BNX2_EMAC_MODE);
3962 val &= ~BNX2_EMAC_MODE_PORT;
3963 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3967 val |= BNX2_EMAC_MODE_PORT_MII;
3969 val |= BNX2_EMAC_MODE_PORT_GMII;
3971 val |= BNX2_EMAC_MODE_25G_MODE;
3974 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3983 val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN;
3985 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
3986 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
3994 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
3995 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3996 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4004 u32 val;
4014 val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
4016 val | BNX2_PORT_FEATURE_ASF_ENABLED);
4018 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);
4028 u32 val;
4033 val = BNX2_RD(bp, BNX2_EMAC_MODE);
4034 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
4035 val &= ~BNX2_EMAC_MODE_MPKT;
4036 BNX2_WR(bp, BNX2_EMAC_MODE, val);
4038 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4039 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4040 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4055 u32 val;
4061 val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
4062 val &= ~BNX2_CONDITION_PM_STATE_MASK;
4063 val |= BNX2_CONDITION_PM_STATE_UNPREP;
4064 bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);
4082 u32 val;
4088 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4089 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4105 u32 val;
4111 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4112 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4128 u32 val;
4130 val = BNX2_RD(bp, BNX2_MISC_CFG);
4131 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4143 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4144 if (val & BNX2_NVM_COMMAND_DONE)
4157 u32 val;
4159 val = BNX2_RD(bp, BNX2_MISC_CFG);
4160 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4167 u32 val;
4169 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4172 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4178 u32 val;
4180 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4183 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4212 u32 val;
4216 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4217 if (val & BNX2_NVM_COMMAND_DONE)
4254 u32 val;
4258 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4259 if (val & BNX2_NVM_COMMAND_DONE) {
4273 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4292 memcpy(&val32, val, 4);
4319 u32 val;
4329 val = BNX2_RD(bp, BNX2_NVM_CFG1);
4333 if (val & 0x40000000) {
4338 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4349 if (val & (1 << 23))
4357 if ((val & mask) == (flash->strapping & mask)) {
4380 } /* if (val & 0x40000000) */
4389 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4390 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4391 if (val)
4392 bp->flash_size = val;
4692 u32 val, sig = 0;
4700 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4701 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4704 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4710 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4741 u32 val;
4755 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4758 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4759 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4760 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4761 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4765 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4766 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4778 u32 val;
4796 val = BNX2_RD(bp, BNX2_MISC_ID);
4803 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4806 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4809 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4814 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4826 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4827 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4833 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4841 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
4842 if (val != 0x01020304) {
4882 u32 val, mtu;
4888 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4897 val |= (0x2 << 20) | (1 << 11);
4900 val |= (1 << 23);
4905 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4907 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
4910 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
4911 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4912 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
4944 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
4945 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4946 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4948 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4950 val |= BNX2_MQ_CONFIG_HALT_DIS;
4953 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
4955 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4956 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4957 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4959 val = (BNX2_PAGE_BITS - 8) << 24;
4960 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
4963 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
4964 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4965 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40;
4966 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
4968 val = bp->mac_addr[0] +
4974 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4978 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4979 if (val > (MAX_ETHERNET_PACKET_SIZE + ETH_HLEN + 4))
4980 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4981 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
5034 val = BNX2_HC_CONFIG_COLLECT_STATS;
5036 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
5044 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
5048 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5050 BNX2_WR(bp, BNX2_HC_CONFIG, val);
5090 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5091 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5092 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5133 u32 val, offset0, offset1, offset2, offset3;
5147 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5148 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5150 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5151 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5153 val = (u64) txr->tx_desc_mapping >> 32;
5154 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5156 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5157 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5221 u32 cid, rx_cid_addr, val;
5238 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5239 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5247 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5248 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5252 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5253 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5255 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5256 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5262 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5263 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5265 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5266 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5306 u32 val;
5341 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5344 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5671 u32 offset, rw_mask, ro_mask, save_val, val;
5685 val = readl(bp->regview + offset);
5686 if ((val & rw_mask) != 0) {
5690 if ((val & ro_mask) != (save_val & ro_mask)) {
5696 val = readl(bp->regview + offset);
5697 if ((val & rw_mask) != rw_mask) {
5701 if ((val & ro_mask) != (save_val & ro_mask)) {
6111 u32 val;
6114 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6115 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6117 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6123 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
7939 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7940 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7950 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7951 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7953 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;