Lines Matching refs:BNX2_WR
269 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
281 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
282 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
308 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
309 BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
318 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
319 BNX2_WR(bp, BNX2_CTX_DATA, val);
495 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
504 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
533 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
552 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
561 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
582 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
599 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
614 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
619 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
623 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
1319 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1322 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1358 BNX2_WR(bp, BNX2_EMAC_MODE, val);
1365 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1373 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
1376 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1967 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1968 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
2296 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2401 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2438 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
2470 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
2573 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
2591 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2594 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2596 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2646 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2647 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2667 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2712 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2717 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2805 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2807 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
3298 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3314 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3362 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3430 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3432 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3471 BNX2_WR(bp, BNX2_HC_COMMAND,
3510 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3548 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3553 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3558 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3598 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3621 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3647 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3650 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3651 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3652 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3793 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3795 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3799 BNX2_WR(bp, addr, val);
3809 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3812 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3815 BNX2_WR(bp, addr, val);
3821 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3824 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3974 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3978 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3981 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
3984 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3985 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
3986 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
3989 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3996 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4036 BNX2_WR(bp, BNX2_EMAC_MODE, val);
4040 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4086 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4108 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4131 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4136 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4137 BNX2_WR(bp, BNX2_NVM_COMMAND,
4160 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4171 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4182 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4202 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4205 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4208 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4244 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4247 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4250 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4290 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4295 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4298 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4301 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4368 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
4369 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
4370 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
4371 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4732 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4734 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4735 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4750 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4760 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4799 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4806 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4814 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4863 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4872 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
4886 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4907 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
4912 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
4924 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4953 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
4956 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4957 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4960 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
4966 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
4974 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4981 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4997 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4999 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
5001 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
5003 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
5005 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
5008 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
5011 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
5014 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
5017 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
5019 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
5021 BNX2_WR(bp, BNX2_HC_COM_TICKS,
5024 BNX2_WR(bp, BNX2_HC_CMD_TICKS,
5028 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
5030 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
5031 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5041 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
5050 BNX2_WR(bp, BNX2_HC_CONFIG, val);
5061 BNX2_WR(bp, base,
5066 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
5070 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
5073 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5077 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5082 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5084 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
5092 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5097 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5239 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5259 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5299 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5310 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5315 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5318 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5332 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5333 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5344 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5836 BNX2_WR(bp, BNX2_HC_COMMAND,
5858 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5862 BNX2_WR(bp, BNX2_HC_COMMAND,
6017 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
6184 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6257 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6258 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6259 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6513 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
6514 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
6516 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6701 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
7709 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7713 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7722 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7726 BNX2_WR(bp, BNX2_EMAC_LED, 0);
7727 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
8146 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
8211 BNX2_WR(bp, PCI_COMMAND, reg);