Lines Matching refs:BNX2_RD
270 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
312 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
492 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
496 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
509 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
513 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
530 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
534 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
549 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
553 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
566 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
579 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
583 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
602 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
1326 val = BNX2_RD(bp, BNX2_EMAC_MODE);
1368 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
1579 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
2435 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
2464 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
2575 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
2600 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
3358 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3369 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3425 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3473 BNX2_RD(bp, BNX2_HC_COMMAND);
3959 val = BNX2_RD(bp, BNX2_EMAC_MODE);
3994 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4033 val = BNX2_RD(bp, BNX2_EMAC_MODE);
4038 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4088 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4111 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4130 val = BNX2_RD(bp, BNX2_MISC_CFG);
4143 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4159 val = BNX2_RD(bp, BNX2_MISC_CFG);
4169 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4180 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4216 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4258 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4260 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
4307 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4329 val = BNX2_RD(bp, BNX2_NVM_CFG1);
4755 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4758 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4761 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4765 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4796 val = BNX2_RD(bp, BNX2_MISC_ID);
4800 BNX2_RD(bp, BNX2_MISC_COMMAND);
4826 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4841 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
4910 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
4944 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
4963 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
5090 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5098 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5102 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
5238 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5839 BNX2_RD(bp, BNX2_HC_COMMAND);
5865 BNX2_RD(bp, BNX2_HC_COMMAND);
6014 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
6018 BNX2_RD(bp, BNX2_HC_COMMAND);
6021 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
6263 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
6508 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
6517 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
6521 cid = BNX2_RD(bp, BNX2_TBDC_CID);
6522 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
6523 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
6544 BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
6545 BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
6547 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6549 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6552 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
7084 *p++ = BNX2_RD(bp, offset);
7708 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
7939 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7979 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
7985 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
8150 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
8209 reg = BNX2_RD(bp, PCI_COMMAND);
8373 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {