Lines Matching refs:val
42 u32 val, u32 off)
44 bcm_writel(val, priv->base + off);
56 u32 val, u32 off)
58 bcm_writel(val, priv->base + off);
67 u16 val, u32 off)
69 bcm_writew(val, priv->base + off);
78 u8 val, u32 off)
80 bcm_writeb(val, priv->base + off);
91 u32 val, u32 off)
93 bcm_writel(val, bcm_enet_shared_base[0] + off);
103 u32 val, u32 off, int chan)
105 bcm_writel(val, bcm_enet_shared_base[1] +
115 u32 val, u32 off, int chan)
117 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
151 u32 tmp, val;
161 val = enet_readl(priv, ENET_MIIDATA_REG);
162 val &= 0xffff;
163 return val;
670 u32 val;
676 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
678 enet_writel(priv, val, ENET_PML_REG(0));
680 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
681 val |= ENET_PMH_DATAVALID_MASK;
682 enet_writel(priv, val, ENET_PMH_REG(0));
694 u32 val;
699 val = enet_readl(priv, ENET_RXCFG_REG);
702 val |= ENET_RXCFG_PROMISC_MASK;
704 val &= ~ENET_RXCFG_PROMISC_MASK;
709 val |= ENET_RXCFG_ALLMCAST_MASK;
711 val &= ~ENET_RXCFG_ALLMCAST_MASK;
715 if (val & ENET_RXCFG_ALLMCAST_MASK) {
716 enet_writel(priv, val, ENET_RXCFG_REG);
743 enet_writel(priv, val, ENET_RXCFG_REG);
751 u32 val;
753 val = enet_readl(priv, ENET_TXCTL_REG);
755 val |= ENET_TXCTL_FD_MASK;
757 val &= ~ENET_TXCTL_FD_MASK;
758 enet_writel(priv, val, ENET_TXCTL_REG);
766 u32 val;
769 val = enet_readl(priv, ENET_RXCFG_REG);
771 val |= ENET_RXCFG_ENFLOW_MASK;
773 val &= ~ENET_RXCFG_ENFLOW_MASK;
774 enet_writel(priv, val, ENET_RXCFG_REG);
780 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
782 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
784 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
785 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
900 u32 val;
1063 val = priv->rx_ring_size / 3;
1064 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1065 val = (priv->rx_ring_size * 2) / 3;
1066 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1076 val = enet_readl(priv, ENET_CTL_REG);
1077 val |= ENET_CTL_ENABLE_MASK;
1078 enet_writel(priv, val, ENET_CTL_REG);
1146 u32 val;
1148 val = enet_readl(priv, ENET_CTL_REG);
1149 val |= ENET_CTL_DISABLE_MASK;
1150 enet_writel(priv, val, ENET_CTL_REG);
1154 u32 val;
1156 val = enet_readl(priv, ENET_CTL_REG);
1157 if (!(val & ENET_CTL_DISABLE_MASK))
1174 u32 val;
1176 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1177 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1361 u32 val;
1368 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1372 *(u64 *)p += val;
1374 *(u32 *)p += val;
1664 u32 val;
1671 val = ENET_CTL_SRESET_MASK;
1672 enet_writel(priv, val, ENET_CTL_REG);
1677 val = enet_readl(priv, ENET_CTL_REG);
1678 if (!(val & ENET_CTL_SRESET_MASK))
1684 val = enet_readl(priv, ENET_CTL_REG);
1686 val |= ENET_CTL_EPHYSEL_MASK;
1688 val &= ~ENET_CTL_EPHYSEL_MASK;
1689 enet_writel(priv, val, ENET_CTL_REG);
1696 val = enet_readl(priv, ENET_MIBCTL_REG);
1697 val |= ENET_MIBCTL_RDCLEAR_MASK;
1698 enet_writel(priv, val, ENET_MIBCTL_REG);
2010 int val, j, up, advertise, lpa, speed, duplex, media;
2023 val = bcmenet_sw_mdio_read(priv, external_phy,
2026 if (val == 0xffff)
2029 up = (val & BMSR_LSTATUS) ? 1 : 0;
2062 if (val & BMSR_ESTATEN) {
2108 u32 val;
2191 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2192 val |= ENETSW_GMCR_RST_MIB_MASK;
2193 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2195 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2196 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2200 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2201 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2202 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2205 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2206 val |= ENETSW_SWMODE_FWD_EN_MASK;
2207 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2244 val = priv->rx_ring_size / 3;
2245 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2246 val = (priv->rx_ring_size * 2) / 3;
2247 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2425 int val)
2431 phy_id, location, val);