Lines Matching refs:ring
144 * DMA ring ops
148 struct bcm4908_enet_dma_ring *ring)
150 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
154 struct bcm4908_enet_dma_ring *ring)
156 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
160 struct bcm4908_enet_dma_ring *ring)
162 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
170 struct bcm4908_enet_dma_ring *ring)
172 int size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
175 ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);
176 if (!ring->cpu_addr)
179 if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {
180 dev_err(dev, "Invalid DMA ring alignment\n");
184 ring->slots = kcalloc(ring->length, sizeof(*ring->slots), GFP_KERNEL);
185 if (!ring->slots)
191 dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);
192 ring->cpu_addr = NULL;
257 struct bcm4908_enet_dma_ring *ring = rings[i];
259 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
260 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
261 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
262 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
299 struct bcm4908_enet_dma_ring *ring)
302 int reset_subch = ring->is_tx ? 1 : 0;
308 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
309 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
310 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
312 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
313 (uint32_t)ring->dma_addr);
315 ring->read_idx = 0;
316 ring->write_idx = 0;
359 struct bcm4908_enet_dma_ring *ring)
361 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
365 struct bcm4908_enet_dma_ring *ring)
367 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
371 struct bcm4908_enet_dma_ring *ring)
373 enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
377 struct bcm4908_enet_dma_ring *ring)
382 enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
386 tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);
389 enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
436 struct bcm4908_enet_dma_ring *ring;
438 ring = (irq == enet->irq_tx) ? &enet->tx_ring : &enet->rx_ring;
440 bcm4908_enet_dma_ring_intrs_off(enet, ring);
441 bcm4908_enet_dma_ring_intrs_ack(enet, ring);
443 napi_schedule(&ring->napi);
524 struct bcm4908_enet_dma_ring *ring = &enet->tx_ring;
533 !(le32_to_cpu(ring->buf_desc[ring->read_idx].ctl) & DMA_CTL_STATUS_OWN))
537 if (ring->read_idx <= ring->write_idx)
538 free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
540 free_buf_descs = ring->read_idx - ring->write_idx;
547 buf_desc = &ring->buf_desc[ring->write_idx];
553 slot = &ring->slots[ring->write_idx];
565 if (ring->write_idx + 1 == ring->length - 1)
575 if (++ring->write_idx == ring->length - 1)
576 ring->write_idx = 0;
645 /* Hardware could disable ring if it run out of descriptors */