Lines Matching refs:value
127 static int atl1_validate_option(int *value, struct atl1_option *opt,
130 if (*value == OPTION_UNSET) {
131 *value = opt->def;
137 switch (*value) {
147 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
149 *value);
159 if (*value == ent->i) {
174 opt->name, *value, opt->err);
175 *value = opt->def;
184 * input. If an invalid value is given, or if no user specified
185 * value exists, a default value is used. The final value is stored
296 u32 value;
297 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
298 if (value & SPI_FLASH_CTRL_EN_VPD) {
299 value &= ~SPI_FLASH_CTRL_EN_VPD;
300 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
303 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
304 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
336 * Reads the value from a PHY register
373 u32 value;
378 value = SPI_FLASH_CTRL_WAIT_READY |
391 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
393 value |= SPI_FLASH_CTRL_START;
394 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
399 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
400 if (!(value & SPI_FLASH_CTRL_START))
404 if (value & SPI_FLASH_CTRL_START)
538 * set hash value for a multicast address
545 u32 crc32, value = 0;
550 value |= (((crc32 >> i) & 1) << (31 - i));
552 return value;
556 * Sets the bit in the multicast table corresponding to the hash value.
558 * hash_value - Multicast address hash value
570 * back the new value. The register is determined by the
571 * upper 7 bits of the hash value and the bit within that
572 * register are determined by the lower 5 bits of the value.
582 * Writes a value to a PHY register
778 * PHY will advertise value(s) parsed from
905 u32 value;
911 value = (((u32) hw->mac_addr[2]) << 24) |
914 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
916 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
917 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
1243 u32 value;
1247 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1250 value |= MAC_CTRL_DUPLX;
1252 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1256 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1258 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1260 value |= (((u32) adapter->hw.preamble_len
1263 __atlx_vlan_mode(netdev->features, &value);
1266 value |= MAC_CTRL_RX_CHKSUM_EN;
1269 value |= MAC_CTRL_BC_EN;
1271 value |= MAC_CTRL_PROMIS_EN;
1273 value |= MAC_CTRL_MC_ALL_EN;
1274 /* value |= MAC_CTRL_LOOPBACK; */
1275 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1392 u32 hi, lo, value;
1395 value = adapter->rfd_ring.count;
1396 hi = value / 16;
1399 lo = value * 7 / 8;
1401 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1403 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1406 value = adapter->rrd_ring.count;
1407 lo = value / 16;
1408 hi = value * 7 / 8;
1411 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1413 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1418 u32 hi, lo, value;
1421 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1422 lo = value / 16;
1425 hi = value * 7 / 8;
1428 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1430 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1433 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1434 lo = value / 8;
1435 hi = value * 7 / 8;
1440 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1442 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1454 u32 value;
1460 value = (((u32) hw->mac_addr[2]) << 24) |
1464 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1465 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1466 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1486 value = adapter->rrd_ring.count;
1487 value <<= 16;
1488 value += adapter->rfd_ring.count;
1489 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1497 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1503 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1506 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1514 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1517 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1524 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1537 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1543 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1559 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1566 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1569 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1573 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1576 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1583 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1586 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1591 value |= (u32) hw->dma_ord;
1593 value |= DMA_CTRL_RCB_VALUE;
1594 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1597 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1599 value <<= 16;
1600 value |= hw->cmb_rrd;
1601 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1602 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1603 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1607 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1608 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1610 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1611 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1612 value = 1; /* config failed */
1614 value = 0;
1619 return value;
1627 u32 value;
1630 value = 0x6500;
1631 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1633 value = ioread32(adapter->hw.hw_addr + 0x1008);
1634 value |= 0x8000;
1635 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1646 unsigned long value;
1648 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1649 if (value & PCI_COMMAND_INTX_DISABLE)
1650 value &= ~PCI_COMMAND_INTX_DISABLE;
1651 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1739 u32 value;
1747 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1753 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1904 u32 value;
2038 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2044 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2678 * @new_mtu: new value for maximum frame size
2705 * Returns 0 on success, negative value on failure
3385 static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3388 adapter->msg_enable = value;