Lines Matching defs:ag71xx_wr
408 static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value)
585 ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
588 ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
596 ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0);
612 ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
614 ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);
675 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
678 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t);
760 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
761 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
762 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
838 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
887 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
888 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
896 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
897 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
901 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
902 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
906 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
907 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
929 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
935 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
938 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
939 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
940 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
941 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
942 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
957 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
960 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
988 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
991 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
992 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
993 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
1001 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1004 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
1025 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
1073 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
1074 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
1075 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
1084 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1);
1400 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
1401 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
1438 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
1571 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
1650 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1717 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1721 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1769 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1773 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1792 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1935 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);