Lines Matching defs:bmwrite
209 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
244 bmwrite(dev, MIFCSR, 0);
248 bmwrite(dev, MIFCSR, 1);
251 bmwrite(dev, MIFCSR, 0);
253 bmwrite(dev, MIFCSR, 1);
265 bmwrite(dev, MIFCSR, b);
267 bmwrite(dev, MIFCSR, b|1);
277 bmwrite(dev, MIFCSR, 4);
282 bmwrite(dev, MIFCSR, 2);
284 bmwrite(dev, MIFCSR, 1);
287 bmwrite(dev, MIFCSR, 4);
295 bmwrite(dev, MIFCSR, 4);
315 bmwrite(dev, RXRST, RxResetValue);
316 bmwrite(dev, TXRST, TxResetBit);
328 bmwrite(dev, XCVRIF, regValue);
332 bmwrite(dev, RSEED, (unsigned short)0x1968);
336 bmwrite(dev, XIFC, regValue);
341 bmwrite(dev, NCCNT, 0);
342 bmwrite(dev, NTCNT, 0);
343 bmwrite(dev, EXCNT, 0);
344 bmwrite(dev, LTCNT, 0);
347 bmwrite(dev, FRCNT, 0);
348 bmwrite(dev, LECNT, 0);
349 bmwrite(dev, AECNT, 0);
350 bmwrite(dev, FECNT, 0);
351 bmwrite(dev, RXCV, 0);
354 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
356 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
357 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
360 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
361 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
363 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
368 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
369 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
370 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
371 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
374 bmwrite(dev, MADD0, *pWord16++);
375 bmwrite(dev, MADD1, *pWord16++);
376 bmwrite(dev, MADD2, *pWord16);
378 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
380 bmwrite(dev, INTDISABLE, EnableNormal);
387 bmwrite(dev, INTDISABLE, DisableAll);
393 bmwrite(dev, INTDISABLE, EnableNormal);
409 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
413 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
477 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
479 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
480 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
533 bmwrite(dev, MADD0, *pWord16++);
534 bmwrite(dev, MADD1, *pWord16++);
535 bmwrite(dev, MADD2, *pWord16);
900 bmwrite(dev, RXCFG, rx_cfg);
917 bmwrite(dev, RXRST, RxResetValue);
918 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
919 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
920 bmwrite(dev, RXCFG, rx_cfg );
927 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
928 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
929 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
930 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
984 bmwrite(dev, RXCFG, rx_cfg);
1014 bmwrite(dev, BHASH0, 0xffff);
1015 bmwrite(dev, BHASH1, 0xffff);
1016 bmwrite(dev, BHASH2, 0xffff);
1017 bmwrite(dev, BHASH3, 0xffff);
1021 bmwrite(dev, RXCFG, rx_cfg);
1027 bmwrite(dev, RXCFG, rx_cfg);
1034 bmwrite(dev, BHASH0, hash_table[0]);
1035 bmwrite(dev, BHASH1, hash_table[1]);
1036 bmwrite(dev, BHASH2, hash_table[2]);
1037 bmwrite(dev, BHASH3, hash_table[3]);
1089 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1096 bmwrite(dev, SROMCSR, ChipSelect);
1110 bmwrite(dev, SROMCSR, data | ChipSelect );
1113 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1116 bmwrite(dev, SROMCSR, data | ChipSelect);
1124 bmwrite(dev, SROMCSR, 0);
1152 bmwrite(dev, SROMCSR, 0);
1203 bmwrite(dev, INTDISABLE, EnableNormal);
1283 bmwrite(dev, INTDISABLE, DisableAll);
1293 bmwrite(dev, INTDISABLE, DisableAll);
1398 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1401 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1403 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1493 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1495 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1532 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1534 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );