Lines Matching refs:reg
149 int reg;
151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
152 reg &= ~XGBE_AN_CL37_INT_MASK;
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
158 int reg;
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
161 reg &= ~XGBE_AN_CL37_INT_MASK;
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
165 reg &= ~XGBE_PCS_CL37_BP;
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
171 int reg;
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
174 reg |= XGBE_PCS_CL37_BP;
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
178 reg |= XGBE_AN_CL37_INT_MASK;
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
366 unsigned int reg;
368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
369 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
372 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
375 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
399 unsigned int reg;
402 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
403 reg &= ~XGBE_KR_TRAINING_ENABLE;
404 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
407 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
408 reg &= ~MDIO_AN_CTRL1_ENABLE;
411 reg |= MDIO_AN_CTRL1_ENABLE;
414 reg |= MDIO_AN_CTRL1_RESTART;
416 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
484 unsigned int ad_reg, lp_reg, reg;
496 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
497 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
499 reg |= pdata->fec_ability;
501 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
507 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
508 reg |= XGBE_KR_TRAINING_ENABLE;
509 reg |= XGBE_KR_TRAINING_START;
510 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
543 unsigned int reg, ad_reg, lp_reg;
546 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
550 if (!(reg & link_support))
657 unsigned int reg;
663 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
664 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
665 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
669 reg &= ~XGBE_AN_CL37_INT_MASK;
670 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
962 unsigned int reg;
967 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
969 reg |= 0x100;
971 reg &= ~0x100;
974 reg |= 0x80;
976 reg &= ~0x80;
979 reg |= XGBE_AN_CL37_FD_MASK;
980 reg &= ~XGBE_AN_CL37_HD_MASK;
982 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
985 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
986 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
987 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
991 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
994 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
1000 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
1002 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
1011 unsigned int reg;
1016 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1018 reg |= 0xc000;
1020 reg &= ~0xc000;
1022 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1025 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1027 reg |= 0x80;
1029 reg &= ~0x80;
1033 reg |= 0x20;
1035 reg &= ~0x20;
1037 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1040 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1042 reg |= 0x400;
1044 reg &= ~0x400;
1047 reg |= 0x800;
1049 reg &= ~0x800;
1052 reg &= ~XGBE_XNP_NP_EXCHANGE;
1054 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);