Lines Matching refs:pdata
129 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
132 if (!pdata->phy_if.phy_impl.module_eeprom)
135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
138 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
141 if (!pdata->phy_if.phy_impl.module_info)
144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
147 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
156 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
169 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
182 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
187 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
192 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
197 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
199 switch (pdata->an_mode) {
202 xgbe_an73_enable_interrupts(pdata);
206 xgbe_an37_enable_interrupts(pdata);
213 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
215 xgbe_an73_clear_interrupts(pdata);
216 xgbe_an37_clear_interrupts(pdata);
219 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
222 pdata->hw_if.set_speed(pdata, SPEED_10000);
225 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
228 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
231 pdata->hw_if.set_speed(pdata, SPEED_2500);
234 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
237 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
240 pdata->hw_if.set_speed(pdata, SPEED_1000);
243 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
246 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
249 if (pdata->kr_redrv)
250 return xgbe_kr_mode(pdata);
253 pdata->hw_if.set_speed(pdata, SPEED_10000);
256 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
259 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
262 pdata->hw_if.set_speed(pdata, SPEED_1000);
265 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
268 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
271 pdata->hw_if.set_speed(pdata, SPEED_1000);
274 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
277 static void xgbe_sgmii_10_mode(struct xgbe_prv_data *pdata)
280 pdata->hw_if.set_speed(pdata, SPEED_10);
283 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_10);
286 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
289 pdata->hw_if.set_speed(pdata, SPEED_1000);
292 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
295 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
297 return pdata->phy_if.phy_impl.cur_mode(pdata);
300 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
302 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
305 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
310 xgbe_kx_1000_mode(pdata);
313 xgbe_kx_2500_mode(pdata);
316 xgbe_kr_mode(pdata);
319 xgbe_sgmii_10_mode(pdata);
322 xgbe_sgmii_100_mode(pdata);
325 xgbe_sgmii_1000_mode(pdata);
328 xgbe_x_mode(pdata);
331 xgbe_sfi_mode(pdata);
336 netif_dbg(pdata, link, pdata->netdev,
341 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
343 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
346 static bool xgbe_set_mode(struct xgbe_prv_data *pdata,
349 if (mode == xgbe_cur_mode(pdata))
352 xgbe_change_mode(pdata, mode);
357 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
360 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
363 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
380 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
382 xgbe_an37_enable_interrupts(pdata);
383 xgbe_an37_set(pdata, true, true);
385 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
388 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
390 xgbe_an37_set(pdata, false, false);
391 xgbe_an37_disable_interrupts(pdata);
393 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
396 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
402 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
404 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
407 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
416 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
419 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
421 xgbe_an73_enable_interrupts(pdata);
422 xgbe_an73_set(pdata, true, true);
424 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
427 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
429 xgbe_an73_set(pdata, false, false);
430 xgbe_an73_disable_interrupts(pdata);
432 pdata->an_start = 0;
434 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
437 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
439 if (pdata->phy_if.phy_impl.an_pre)
440 pdata->phy_if.phy_impl.an_pre(pdata);
442 switch (pdata->an_mode) {
445 xgbe_an73_restart(pdata);
449 xgbe_an37_restart(pdata);
456 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
458 if (pdata->phy_if.phy_impl.an_post)
459 pdata->phy_if.phy_impl.an_post(pdata);
461 switch (pdata->an_mode) {
464 xgbe_an73_disable(pdata);
468 xgbe_an37_disable(pdata);
475 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
477 xgbe_an73_disable(pdata);
478 xgbe_an37_disable(pdata);
481 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
489 if (!xgbe_in_kr_mode(pdata))
493 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
494 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
496 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
499 reg |= pdata->fec_ability;
501 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
504 if (pdata->phy_if.phy_impl.kr_training_pre)
505 pdata->phy_if.phy_impl.kr_training_pre(pdata);
507 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
510 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
511 pdata->kr_start_time = jiffies;
513 netif_dbg(pdata, link, pdata->netdev,
516 if (pdata->phy_if.phy_impl.kr_training_post)
517 pdata->phy_if.phy_impl.kr_training_post(pdata);
522 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
532 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
533 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
534 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
539 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
546 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
549 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
554 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
555 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
559 ? xgbe_an73_tx_xnp(pdata, state)
560 : xgbe_an73_tx_training(pdata, state);
563 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
569 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
570 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
574 ? xgbe_an73_tx_xnp(pdata, state)
575 : xgbe_an73_tx_training(pdata, state);
578 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
584 if (!pdata->an_start) {
585 pdata->an_start = jiffies;
587 an_timeout = pdata->an_start +
591 pdata->kr_state = XGBE_RX_BPA;
592 pdata->kx_state = XGBE_RX_BPA;
594 pdata->an_start = jiffies;
596 netif_dbg(pdata, link, pdata->netdev,
601 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
602 : &pdata->kx_state;
606 ret = xgbe_an73_rx_bpa(pdata, state);
610 ret = xgbe_an73_rx_xnp(pdata, state);
620 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
622 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
625 if (xgbe_in_kr_mode(pdata)) {
626 pdata->kr_state = XGBE_RX_ERROR;
632 if (pdata->kx_state != XGBE_RX_BPA)
635 pdata->kx_state = XGBE_RX_ERROR;
640 if (pdata->kr_state != XGBE_RX_BPA)
644 xgbe_an_disable(pdata);
646 xgbe_switch_mode(pdata);
648 pdata->an_result = XGBE_AN_READY;
650 xgbe_an_restart(pdata);
655 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
660 xgbe_an37_disable_interrupts(pdata);
663 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
664 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
665 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
667 if (pdata->an_int) {
670 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
672 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
675 xgbe_an37_enable_interrupts(pdata);
678 if (pdata->vdata->irq_reissue_support)
679 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
683 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
686 xgbe_an73_disable_interrupts(pdata);
689 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
691 if (pdata->an_int) {
693 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
695 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
698 xgbe_an73_enable_interrupts(pdata);
701 if (pdata->vdata->irq_reissue_support)
702 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
708 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_an);
710 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
712 switch (pdata->an_mode) {
715 xgbe_an73_isr(pdata);
719 xgbe_an37_isr(pdata);
728 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
730 if (pdata->isr_as_tasklet)
731 tasklet_schedule(&pdata->tasklet_an);
733 xgbe_an_isr_task(&pdata->tasklet_an);
738 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
740 xgbe_an_isr_task(&pdata->tasklet_an);
747 struct xgbe_prv_data *pdata = container_of(work,
754 flush_work(&pdata->an_work);
755 queue_work(pdata->an_workqueue, &pdata->an_work);
778 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
780 enum xgbe_an cur_state = pdata->an_state;
782 if (!pdata->an_int)
785 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
786 pdata->an_state = XGBE_AN_COMPLETE;
787 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
790 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
791 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
792 pdata->an_state = XGBE_AN_NO_LINK;
795 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
796 xgbe_state_as_string(pdata->an_state));
798 cur_state = pdata->an_state;
800 switch (pdata->an_state) {
805 netif_dbg(pdata, link, pdata->netdev,
813 pdata->an_state = XGBE_AN_ERROR;
816 if (pdata->an_state == XGBE_AN_ERROR) {
817 netdev_err(pdata->netdev,
821 pdata->an_int = 0;
822 xgbe_an37_clear_interrupts(pdata);
825 if (pdata->an_state >= XGBE_AN_COMPLETE) {
826 pdata->an_result = pdata->an_state;
827 pdata->an_state = XGBE_AN_READY;
829 if (pdata->phy_if.phy_impl.an_post)
830 pdata->phy_if.phy_impl.an_post(pdata);
832 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
833 xgbe_state_as_string(pdata->an_result));
836 xgbe_an37_enable_interrupts(pdata);
839 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
841 enum xgbe_an cur_state = pdata->an_state;
843 if (!pdata->an_int)
847 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
848 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
849 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
850 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
851 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
852 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
853 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
854 pdata->an_state = XGBE_AN_COMPLETE;
855 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
857 pdata->an_state = XGBE_AN_ERROR;
861 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
862 xgbe_state_as_string(pdata->an_state));
864 cur_state = pdata->an_state;
866 switch (pdata->an_state) {
868 pdata->an_supported = 0;
872 pdata->an_state = xgbe_an73_page_received(pdata);
873 pdata->an_supported++;
877 pdata->an_supported = 0;
878 pdata->parallel_detect = 0;
879 pdata->an_state = xgbe_an73_incompat_link(pdata);
883 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
884 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
885 pdata->an_supported ? "Auto negotiation"
893 pdata->an_state = XGBE_AN_ERROR;
896 if (pdata->an_state == XGBE_AN_NO_LINK) {
897 pdata->an_int = 0;
898 xgbe_an73_clear_interrupts(pdata);
899 } else if (pdata->an_state == XGBE_AN_ERROR) {
900 netdev_err(pdata->netdev,
904 pdata->an_int = 0;
905 xgbe_an73_clear_interrupts(pdata);
908 if (pdata->an_state >= XGBE_AN_COMPLETE) {
909 pdata->an_result = pdata->an_state;
910 pdata->an_state = XGBE_AN_READY;
911 pdata->kr_state = XGBE_RX_BPA;
912 pdata->kx_state = XGBE_RX_BPA;
913 pdata->an_start = 0;
915 if (pdata->phy_if.phy_impl.an_post)
916 pdata->phy_if.phy_impl.an_post(pdata);
918 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
919 xgbe_state_as_string(pdata->an_result));
922 if (cur_state != pdata->an_state)
925 if (pdata->an_int)
928 xgbe_an73_enable_interrupts(pdata);
933 struct xgbe_prv_data *pdata = container_of(work,
937 mutex_lock(&pdata->an_mutex);
939 switch (pdata->an_mode) {
942 xgbe_an73_state_machine(pdata);
946 xgbe_an37_state_machine(pdata);
953 if (pdata->vdata->irq_reissue_support)
954 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
956 mutex_unlock(&pdata->an_mutex);
959 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
964 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
967 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
982 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
985 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
989 switch (pdata->an_mode) {
1002 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
1004 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
1005 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
1008 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
1013 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
1016 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1022 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1025 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1037 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1040 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1054 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1056 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1059 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1062 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1063 switch (pdata->an_mode) {
1066 xgbe_an73_init(pdata);
1070 xgbe_an37_init(pdata);
1077 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1079 if (pdata->tx_pause && pdata->rx_pause)
1081 else if (pdata->rx_pause)
1083 else if (pdata->tx_pause)
1109 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1111 if (pdata->phy.link)
1112 netdev_info(pdata->netdev,
1114 xgbe_phy_speed_string(pdata->phy.speed),
1115 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1116 xgbe_phy_fc_string(pdata));
1118 netdev_info(pdata->netdev, "Link is Down\n");
1121 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1125 if (pdata->phy.link) {
1127 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1129 if (pdata->tx_pause != pdata->phy.tx_pause) {
1131 pdata->tx_pause = pdata->phy.tx_pause;
1132 pdata->hw_if.config_tx_flow_control(pdata);
1135 if (pdata->rx_pause != pdata->phy.rx_pause) {
1137 pdata->rx_pause = pdata->phy.rx_pause;
1138 pdata->hw_if.config_rx_flow_control(pdata);
1142 if (pdata->phy_speed != pdata->phy.speed) {
1144 pdata->phy_speed = pdata->phy.speed;
1147 if (pdata->phy_link != pdata->phy.link) {
1149 pdata->phy_link = pdata->phy.link;
1151 } else if (pdata->phy_link) {
1153 pdata->phy_link = 0;
1154 pdata->phy_speed = SPEED_UNKNOWN;
1157 if (new_state && netif_msg_link(pdata))
1158 xgbe_phy_print_status(pdata);
1161 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1163 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1166 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1170 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1173 xgbe_an_disable(pdata);
1176 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1193 if (pdata->phy.duplex != DUPLEX_FULL)
1206 xgbe_change_mode(pdata, mode);
1208 xgbe_set_mode(pdata, mode);
1213 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode)
1217 mutex_lock(&pdata->an_mutex);
1219 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1220 pdata->link_check = jiffies;
1222 ret = pdata->phy_if.phy_impl.an_config(pdata);
1226 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1227 ret = xgbe_phy_config_fixed(pdata);
1228 if (ret || !pdata->kr_redrv)
1231 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1233 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1237 disable_irq(pdata->an_irq);
1241 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1242 xgbe_set_mode(pdata, XGBE_MODE_KR);
1243 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1244 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1245 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1246 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1247 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1248 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1249 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1250 xgbe_set_mode(pdata, XGBE_MODE_X);
1251 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1252 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1253 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1254 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1255 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1256 xgbe_set_mode(pdata, XGBE_MODE_SGMII_10);
1258 enable_irq(pdata->an_irq);
1265 xgbe_an_disable_all(pdata);
1268 xgbe_an_clear_interrupts_all(pdata);
1270 pdata->an_result = XGBE_AN_READY;
1271 pdata->an_state = XGBE_AN_READY;
1272 pdata->kr_state = XGBE_RX_BPA;
1273 pdata->kx_state = XGBE_RX_BPA;
1276 enable_irq(pdata->an_irq);
1278 xgbe_an_init(pdata);
1279 xgbe_an_restart(pdata);
1283 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1285 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1287 mutex_unlock(&pdata->an_mutex);
1292 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1294 return __xgbe_phy_config_aneg(pdata, true);
1297 static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata)
1299 return __xgbe_phy_config_aneg(pdata, false);
1302 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1304 return (pdata->an_result == XGBE_AN_COMPLETE);
1307 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1313 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1315 if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) &&
1316 pdata->phy.autoneg == AUTONEG_ENABLE) {
1324 kr_time = pdata->kr_start_time +
1329 if (pdata->an_result == XGBE_AN_COMPLETE)
1334 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1335 xgbe_phy_config_aneg(pdata);
1339 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1341 return pdata->phy_if.phy_impl.an_outcome(pdata);
1344 static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1346 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1351 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1352 mode = xgbe_cur_mode(pdata);
1354 mode = xgbe_phy_status_aneg(pdata);
1358 pdata->phy.speed = SPEED_10;
1361 pdata->phy.speed = SPEED_100;
1366 pdata->phy.speed = SPEED_1000;
1369 pdata->phy.speed = SPEED_2500;
1373 pdata->phy.speed = SPEED_10000;
1377 pdata->phy.speed = SPEED_UNKNOWN;
1380 pdata->phy.duplex = DUPLEX_FULL;
1382 if (!xgbe_set_mode(pdata, mode))
1385 if (pdata->an_again)
1386 xgbe_phy_reconfig_aneg(pdata);
1391 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1396 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1397 netif_carrier_off(pdata->netdev);
1399 pdata->phy.link = 0;
1403 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1405 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1408 xgbe_phy_config_aneg(pdata);
1412 if (pdata->phy.link) {
1413 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1414 xgbe_check_link_timeout(pdata);
1418 if (xgbe_phy_status_result(pdata))
1421 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1422 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1424 netif_carrier_on(pdata->netdev);
1426 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1427 xgbe_check_link_timeout(pdata);
1433 xgbe_phy_status_result(pdata);
1435 netif_carrier_off(pdata->netdev);
1439 xgbe_phy_adjust_link(pdata);
1442 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1444 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1446 if (!pdata->phy_started)
1450 pdata->phy_started = 0;
1453 xgbe_an_disable_all(pdata);
1455 if (pdata->dev_irq != pdata->an_irq) {
1456 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1457 tasklet_kill(&pdata->tasklet_an);
1460 pdata->phy_if.phy_impl.stop(pdata);
1462 pdata->phy.link = 0;
1464 xgbe_phy_adjust_link(pdata);
1467 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1469 struct net_device *netdev = pdata->netdev;
1472 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1474 ret = pdata->phy_if.phy_impl.start(pdata);
1479 if (pdata->dev_irq != pdata->an_irq) {
1480 tasklet_setup(&pdata->tasklet_an, xgbe_an_isr_task);
1482 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1483 xgbe_an_isr, 0, pdata->an_name,
1484 pdata);
1494 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1495 xgbe_kr_mode(pdata);
1496 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1497 xgbe_kx_2500_mode(pdata);
1498 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1499 xgbe_kx_1000_mode(pdata);
1500 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1501 xgbe_sfi_mode(pdata);
1502 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1503 xgbe_x_mode(pdata);
1504 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1505 xgbe_sgmii_1000_mode(pdata);
1506 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1507 xgbe_sgmii_100_mode(pdata);
1508 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1509 xgbe_sgmii_10_mode(pdata);
1516 pdata->phy_started = 1;
1518 xgbe_an_init(pdata);
1519 xgbe_an_enable_interrupts(pdata);
1521 return xgbe_phy_config_aneg(pdata);
1524 if (pdata->dev_irq != pdata->an_irq)
1525 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1528 pdata->phy_if.phy_impl.stop(pdata);
1533 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1537 ret = pdata->phy_if.phy_impl.reset(pdata);
1542 xgbe_an_disable_all(pdata);
1545 xgbe_an_clear_interrupts_all(pdata);
1550 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1552 struct device *dev = pdata->dev;
1557 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1559 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1561 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1563 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1565 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1567 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1570 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1572 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1575 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1578 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1581 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1584 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1589 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1591 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1613 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1615 pdata->phy_if.phy_impl.exit(pdata);
1618 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1620 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1623 mutex_init(&pdata->an_mutex);
1624 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1625 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1626 pdata->mdio_mmd = MDIO_MMD_PCS;
1629 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1631 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1635 ret = pdata->phy_if.phy_impl.init(pdata);
1642 pdata->phy.address = 0;
1645 pdata->phy.autoneg = AUTONEG_ENABLE;
1646 pdata->phy.speed = SPEED_UNKNOWN;
1647 pdata->phy.duplex = DUPLEX_UNKNOWN;
1649 pdata->phy.autoneg = AUTONEG_DISABLE;
1650 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1651 pdata->phy.duplex = DUPLEX_FULL;
1654 pdata->phy.link = 0;
1656 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1657 pdata->phy.tx_pause = pdata->tx_pause;
1658 pdata->phy.rx_pause = pdata->rx_pause;
1664 if (pdata->rx_pause) {
1669 if (pdata->tx_pause) {
1677 if (netif_msg_drv(pdata))
1678 xgbe_dump_phy_registers(pdata);