Lines Matching defs:fifo

2396 						  unsigned int *fifo)
2402 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT;
2422 /* The configured value may not be the actual amount of fifo RAM */
2429 /* The configured value may not be the actual amount of fifo RAM */
2436 unsigned int *fifo)
2444 /* Calculate the fifo setting by dividing the queue's fifo size
2445 * by the fifo allocation increment (with 0 representing the
2452 /* Distribute the fifo equally amongst the queues */
2454 fifo[i] = p_fifo;
2459 unsigned int *fifo)
2470 * don't require a large fifo
2473 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1;
2527 unsigned int *fifo)
2540 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2544 /* Calculate how much fifo we have to play with */
2547 /* Calculate how much more than base fifo PFC needs, which also
2560 /* Calculate DCB fifo settings:
2561 * - distribute remaining fifo between the VLAN priority
2569 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1;
2576 "RXq%u cannot set needed fifo size\n", i);
2583 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT);
2590 /* Distribute remaining fifo across queues */
2592 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT);
2599 unsigned int fifo[XGBE_MAX_QUEUES];
2604 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
2607 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]);
2610 "%d Tx hardware queues, %d byte fifo per queue\n",
2611 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2617 unsigned int fifo[XGBE_MAX_QUEUES];
2621 /* Clear any DCB related fifo/queue information */
2628 /* Assign a minimum fifo to the non-VLAN priority queues */
2629 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
2632 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo);
2634 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2637 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
2639 xgbe_calculate_flow_control_threshold(pdata, fifo);
2647 "RxQ%u, %u byte fifo queue\n", i,
2648 ((fifo[i] + 1) * XGMAC_FIFO_UNIT));
2651 "%u Rx hardware queues, %u byte fifo per queue\n",
2653 ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2836 /* Just stop the Tx queues while Rx fifo is changed */
2839 /* Suspend Rx so that fifo's can be adjusted */
3277 * packets. Wait for the Tx queue to empty the Tx fifo. Don't
3391 * packets. Wait for the Rx queue to empty the Rx fifo. Don't