Lines Matching defs:channel
192 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
195 if (pdata->channel[i]->tx_ring)
196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
199 if (pdata->channel[i]->rx_ring)
200 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,
212 if (!pdata->channel[i]->tx_ring)
215 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,
269 if (!pdata->channel[i]->rx_ring)
272 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT,
289 if (!pdata->channel[i]->rx_ring)
292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ,
302 if (!pdata->channel[i]->tx_ring)
305 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1);
314 if (!pdata->channel[i]->rx_ring)
317 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1);
659 struct xgbe_channel *channel;
670 channel = pdata->channel[i];
673 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR,
674 XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
677 channel->curr_ier = 0;
685 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1);
686 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1);
688 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1);
689 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1);
691 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
693 if (channel->tx_ring) {
696 * per channel interrupts in edge triggered
700 XGMAC_SET_BITS(channel->curr_ier,
703 if (channel->rx_ring) {
707 * per channel interrupts in edge triggered
710 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
712 XGMAC_SET_BITS(channel->curr_ier,
716 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
1465 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1467 struct xgbe_ring *ring = channel->tx_ring;
1483 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1487 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1489 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1543 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1545 struct xgbe_prv_data *pdata = channel->pdata;
1546 struct xgbe_ring *ring = channel->rx_ring;
1562 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1566 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1568 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1573 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1698 static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1701 struct xgbe_prv_data *pdata = channel->pdata;
1710 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1714 if (pdata->tx_usecs && !channel->tx_timer_active) {
1715 channel->tx_timer_active = 1;
1716 mod_timer(&channel->tx_timer,
1723 static void xgbe_dev_xmit(struct xgbe_channel *channel)
1725 struct xgbe_prv_data *pdata = channel->pdata;
1726 struct xgbe_ring *ring = channel->tx_ring;
1925 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets;
1926 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes;
1949 channel->queue_index)))
1950 xgbe_tx_start_xmit(channel, ring);
1955 channel->name, start_index & (ring->rdesc_count - 1),
1961 static int xgbe_dev_read(struct xgbe_channel *channel)
1963 struct xgbe_prv_data *pdata = channel->pdata;
1964 struct xgbe_ring *ring = channel->rx_ring;
2112 pdata->ext_stats.rxq_packets[channel->queue_index]++;
2113 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len;
2115 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
2133 static int xgbe_enable_int(struct xgbe_channel *channel,
2138 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
2141 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1);
2144 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1);
2147 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
2150 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
2153 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1);
2156 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
2157 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
2160 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
2163 channel->curr_ier |= channel->saved_ier;
2169 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
2174 static int xgbe_disable_int(struct xgbe_channel *channel,
2179 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
2182 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0);
2185 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0);
2188 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
2191 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0);
2194 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0);
2197 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
2198 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
2201 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0);
2204 channel->saved_ier = channel->curr_ier;
2205 channel->curr_ier = 0;
2211 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
2722 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
3335 "timed out waiting for Tx DMA channel %u to stop\n",
3343 /* Enable each Tx DMA channel */
3345 if (!pdata->channel[i]->tx_ring)
3348 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
3364 /* Prepare for Tx DMA channel stop */
3375 /* Disable each Tx DMA channel */
3377 if (!pdata->channel[i]->tx_ring)
3380 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
3414 /* Enable each Rx DMA channel */
3416 if (!pdata->channel[i]->rx_ring)
3419 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
3445 /* Prepare for Rx DMA channel stop */
3452 /* Disable each Rx DMA channel */
3454 if (!pdata->channel[i]->rx_ring)
3457 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
3465 /* Enable each Tx DMA channel */
3467 if (!pdata->channel[i]->tx_ring)
3470 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
3481 /* Prepare for Tx DMA channel stop */
3488 /* Disable each Tx DMA channel */
3490 if (!pdata->channel[i]->tx_ring)
3493 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
3501 /* Enable each Rx DMA channel */
3503 if (!pdata->channel[i]->rx_ring)
3506 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
3514 /* Disable each Rx DMA channel */
3516 if (!pdata->channel[i]->rx_ring)
3519 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);