Lines Matching refs:REGA
165 #define REGA(a) (*( AREG = (a), &DREG ))
355 REGA(CSR0) = CSR0_STOP;
419 REGA(CSR0) = CSR0_STOP;
424 REGA(CSR0) = CSR0_INIT;
497 REGA(CSR1) = dvma_vtob(&(MEM->init));
498 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
501 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON;
503 REGA(CSR3) = CSR3_BSWP;
533 REGA(CSR3) = CSR3_BSWP;
555 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
585 REGA( CSR0 ) = CSR0_STOP;
587 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT;
631 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT;
703 REGA(CSR0) = CSR0_STOP;
704 REGA(CSR3) = CSR3_BSWP;
706 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
741 REGA(CSR0) = CSR0_STOP;
742 REGA(CSR3) = CSR3_BSWP;
744 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
752 REGA(CSR0) = CSR0_INEA;
896 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
906 REGA( CSR8+i ) = multicast_table[i];
907 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
914 REGA( CSR3 ) = CSR3_BSWP;
917 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;