Lines Matching refs:IntLatch
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
1702 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1708 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1899 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
2270 if ((status & IntLatch) == 0)
2345 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2351 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2352 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2388 if ((status & IntLatch) == 0)
2481 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2487 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2491 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);