Lines Matching defs:EL3_CMD
438 #define EL3_CMD 0x0e
441 /* The top five bits written to EL3_CMD are a command, the lower
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
663 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
945 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
1494 iowrite16(cmd, ioaddr + EL3_CMD);
1627 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1651 iowrite16(StartCoax, ioaddr + EL3_CMD);
1661 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1674 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1693 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1695 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1696 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1706 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1709 ioaddr + EL3_CMD);
1710 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1864 ioaddr + EL3_CMD);
1879 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1923 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1930 iowrite16(TxEnable, ioaddr + EL3_CMD);
1973 iowrite16(TxEnable, ioaddr + EL3_CMD);
1978 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1993 ioaddr + EL3_CMD);
1999 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2000 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2029 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2030 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2036 iowrite16(TxEnable, ioaddr + EL3_CMD);
2069 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2081 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2102 iowrite16(TxEnable, ioaddr + EL3_CMD);
2236 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2300 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2319 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2343 ioaddr + EL3_CMD);
2344 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2345 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2351 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2411 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2420 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2479 ioaddr + EL3_CMD);
2480 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2481 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2487 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2561 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2570 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2679 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2697 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2700 iowrite16(RxDisable, ioaddr + EL3_CMD);
2701 iowrite16(TxDisable, ioaddr + EL3_CMD);
2708 iowrite16(StopCoax, ioaddr + EL3_CMD);
2710 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2819 iowrite16(DownUnstall, ioaddr + EL3_CMD);
3069 iowrite16(new_mode, ioaddr + EL3_CMD);
3237 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3238 iowrite16(RxEnable, ioaddr + EL3_CMD);
3280 vp->ioaddr + EL3_CMD);
3338 iowrite16(TotalReset, ioaddr + EL3_CMD);