Lines Matching refs:val
404 u32 addr, val;
420 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
424 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
427 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
433 ret = regmap_read(priv->map, addr + (i - 1), &val);
436 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
444 u32 val;
450 val = BIT(line) | BIT(line + 6);
452 val = BIT(line);
453 return val;
547 u32 val;
565 &val);
577 val = 0;
582 val = RTL8366RB_INTERRUPT_POLARITY;
587 val);
620 u16 val;
627 val = addr[0] << 8 | addr[1];
628 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
631 val = addr[2] << 8 | addr[3];
632 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
635 val = addr[4] << 8 | addr[5];
636 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
648 u16 val;
771 u32 val;
779 &val);
782 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
792 jam_table[i].val,
796 jam_table[i].val);
811 u32 val;
1011 val = RTL8366RB_LED_OFF;
1014 val = RTL8366RB_LED_FORCE;
1020 val << (i * 4));
1140 u16 val = enable ? 0x3f : 0;
1150 0x3F, val);
1156 val << RTL8366RB_LED_1_OFFSET);
1161 0x3F, val);
1167 val << RTL8366RB_LED_3_OFFSET);
1348 (flags.val & BR_LEARNING) ? 0 : BIT(port));
1360 u32 val;
1365 val = RTL8366RB_STP_STATE_DISABLED;
1369 val = RTL8366RB_STP_STATE_BLOCKING;
1372 val = RTL8366RB_STP_STATE_LEARNING;
1375 val = RTL8366RB_STP_STATE_FORWARDING;
1386 RTL8366RB_STP_STATE(port, val));
1593 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1606 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1675 u32 val;
1700 &val);
1704 ret = val;
1706 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1707 phy, regnum, reg, val);
1716 u16 val)
1733 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1734 phy, regnum, reg, val);
1736 ret = regmap_write(priv->map_nolock, reg, val);
1752 u16 val)
1754 return rtl8366rb_phy_write(ds->priv, phy, regnum, val);
1760 u32 val;
1767 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1771 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1787 u32 val;
1790 ret = regmap_read(priv->map, 0x5c, &val);
1796 switch (val) {
1811 val);