Lines Matching refs:port
46 /* Switch per-port learning disablement register */
83 /* bits 0..7 = port 0, bits 8..15 = port 1 */
85 /* bits 0..7 = port 2, bits 8..15 = port 3 */
87 /* bits 0..7 = port 4, bits 8..15 = port 5 */
104 /* bits 0..7 = port 0, bits 8..15 = port 1 */
106 /* bits 0..7 = port 2, bits 8..15 = port 3 */
108 /* bits 0..7 = port 4, bits 8..15 = port 5 */
113 /* Spanning tree status (STP) control, two bits per port per FID */
120 #define RTL8366RB_STP_STATE(port, state) \
121 ((state) << ((port) * 2))
122 #define RTL8366RB_STP_STATE_MASK(port) \
123 RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
125 /* CPU port control reg */
162 /* VLAN Ingress Control Register 1, one bit per port.
165 * port.
167 * a C-tag with VID != 0 for respective port.
170 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))
172 /* VLAN Ingress Control Register 2, one bit per port.
174 * a VLAN classification that does not include the port is in its
252 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
253 #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
254 #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
255 #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
256 #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
258 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
355 * @max_mtu: per-port max MTU setting
356 * @pvid_enabled: if PVID is set for respective port
400 int port,
409 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
879 /* Isolate all user ports so they can only send packets to itself and the CPU port */
887 /* CPU port can send packets to all ports */
919 /* Enable CPU port with custom DSA tag 8899.
930 /* Make sure we default-enable the fixed CPU port */
958 /* Port 4 setup: this enables Port 4, usually the WAN port,
960 * the port is initialized to. There is no explanation of the
961 * IO modes in the Realtek source code, if your WAN port is
995 * Each port has 4 LEDs, we configure all ports to the same
1045 int port,
1052 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1058 if (port == priv->cpu_port) {
1069 /* RSGMII port, but we don't have that, and we don't
1079 rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1086 if (port != priv->cpu_port)
1089 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1091 /* Force the fixed CPU port into 1Gbit mode, no autonegotiation */
1093 BIT(port), BIT(port));
1095 dev_err(priv->dev, "failed to force 1Gbit on CPU port\n");
1103 dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1107 /* Enable the CPU port */
1108 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1111 dev_err(priv->dev, "failed to enable the CPU port\n");
1117 rtl8366rb_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1123 if (port != priv->cpu_port)
1126 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1128 /* Disable the CPU port */
1129 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1130 BIT(port));
1132 dev_err(priv->dev, "failed to disable the CPU port\n");
1138 int port, bool enable)
1146 switch (port) {
1176 dev_err(priv->dev, "no LED for port %d\n", port);
1180 dev_err(priv->dev, "error updating LED on port %d\n", port);
1184 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1190 dev_dbg(priv->dev, "enable port %d\n", port);
1191 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1196 rb8366rb_set_port_led(priv, port, true);
1201 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1206 dev_dbg(priv->dev, "disable port %d\n", port);
1207 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1208 BIT(port));
1212 rb8366rb_set_port_led(priv, port, false);
1216 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1227 /* Current port handled last */
1228 if (i == port)
1233 /* Join this port to each other port on the bridge */
1235 RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1236 RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1238 dev_err(priv->dev, "failed to join port %d\n", port);
1244 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1250 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1259 /* Current port handled last */
1260 if (i == port)
1265 /* Remove this port from any other port on the bridge */
1267 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);
1269 dev_err(priv->dev, "failed to leave port %d\n", port);
1275 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1282 * @port: the port to drop untagged and C-tagged frames on
1287 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1290 RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1291 drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1294 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1304 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1307 /* If the port is not in the member set, the frame will be dropped */
1309 BIT(port), vlan_filtering ? BIT(port) : 0);
1315 * filtering on a port, we need to accept any frames.
1318 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1320 ret = rtl8366rb_drop_untagged(priv, port, false);
1326 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1338 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1347 BIT(port),
1348 (flags.val & BR_LEARNING) ? 0 : BIT(port));
1357 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1382 /* Set the same status for the port on all the FIDs */
1385 RTL8366RB_STP_STATE_MASK(port),
1386 RTL8366RB_STP_STATE(port, val));
1391 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1397 BIT(port), BIT(port));
1400 BIT(port), 0);
1403 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1411 /* Cache the per-port MTU setting */
1413 rb->max_mtu[port] = new_mtu;
1416 * common denominator: the biggest set for any one port will
1445 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1593 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1598 if (port >= priv->num_ports)
1601 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1606 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1612 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1621 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1624 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1626 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1628 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1632 rb->pvid_enabled[port] = pvid_enabled;
1638 if (dsa_port_is_vlan_filtering(dsa_to_port(priv->ds, port)))
1639 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);