Lines Matching refs:rules
53 * 3 control rules for phy0-3 that applies to all their leds
54 * 3 control rules for phy4
65 qca8k_parse_netdev(unsigned long rules, u32 *offload_trigger)
68 if (test_bit(TRIGGER_NETDEV_TX, &rules))
70 if (test_bit(TRIGGER_NETDEV_RX, &rules))
72 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
74 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
76 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
78 if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
80 if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
83 if (rules && !*offload_trigger)
278 qca8k_cled_hw_control_is_supported(struct led_classdev *ldev, unsigned long rules)
282 return qca8k_parse_netdev(rules, &offload_trigger);
286 qca8k_cled_hw_control_set(struct led_classdev *ldev, unsigned long rules)
294 ret = qca8k_parse_netdev(rules, &offload_trigger);
310 qca8k_cled_hw_control_get(struct led_classdev *ldev, unsigned long *rules)
333 set_bit(TRIGGER_NETDEV_TX, rules);
335 set_bit(TRIGGER_NETDEV_RX, rules);
337 set_bit(TRIGGER_NETDEV_LINK_10, rules);
339 set_bit(TRIGGER_NETDEV_LINK_100, rules);
341 set_bit(TRIGGER_NETDEV_LINK_1000, rules);
343 set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
345 set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);