Lines Matching refs:port
249 struct ar9331_sw_port port[AR9331_SW_PORTS];
252 static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port)
254 struct ar9331_sw_port *p = port - port->idx;
257 offsetof(struct ar9331_sw_priv, port));
293 static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum,
304 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
323 static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum)
334 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
392 static int ar9331_sw_setup_port(struct dsa_switch *ds, int port)
399 /* Generate default port settings */
403 if (dsa_is_cpu_port(ds, port)) {
404 /* CPU port should be allowed to communicate with all user
408 /* Enable Atheros header on CPU port. This will allow us
409 * communicate with each port separately
412 } else if (dsa_is_user_port(ds, port)) {
413 /* User ports should communicate only with the CPU port.
415 port_mask = BIT(dsa_upstream_port(ds, port));
425 ret = regmap_write(regmap, AR9331_SW_REG_PORT_VLAN(port), val);
429 ret = regmap_write(regmap, AR9331_SW_REG_PORT_CTRL(port), port_ctrl);
485 static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)
491 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0);
497 int port,
503 static void ar9331_sw_phylink_get_caps(struct dsa_switch *ds, int port,
509 switch (port) {
526 static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port,
534 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
541 static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port,
546 struct ar9331_sw_port *p = &priv->port[port];
550 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
558 static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port,
566 struct ar9331_sw_port *p = &priv->port[port];
597 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
605 static void ar9331_read_stats(struct ar9331_sw_port *port)
607 struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port);
608 struct ethtool_pause_stats *pstats = &port->pause_stats;
609 struct rtnl_link_stats64 *stats = &port->stats;
614 ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx),
622 spin_lock(&port->stats_lock);
652 spin_unlock(&port->stats_lock);
657 struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port,
660 ar9331_read_stats(port);
662 schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES);
665 static void ar9331_get_stats64(struct dsa_switch *ds, int port,
669 struct ar9331_sw_port *p = &priv->port[port];
676 static void ar9331_get_pause_stats(struct dsa_switch *ds, int port,
680 struct ar9331_sw_port *p = &priv->port[port];
1064 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1065 struct ar9331_sw_port *port = &priv->port[i];
1067 port->idx = i;
1068 spin_lock_init(&port->stats_lock);
1069 INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll);
1092 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1093 struct ar9331_sw_port *port = &priv->port[i];
1095 cancel_delayed_work_sync(&port->mib_read);