Lines Matching refs:val
22 u16 *val)
26 return mv88e6xxx_read(chip, addr, reg, val);
30 int bit, int val)
34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val);
38 u16 val)
42 return mv88e6xxx_write(chip, addr, reg, val);
971 u16 val;
974 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
979 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
981 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
983 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
989 u16 val;
992 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
996 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK;
999 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT |
1002 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT;
1004 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
1516 u16 val;
1527 val = MV88E6393X_PORT_EPC_CMD_BUSY |
1531 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
1611 u16 *mask, u16 *val, int *shift)
1652 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
1655 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
1658 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
1661 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
1674 u16 reg, mask, val;
1679 &val, &shift);
1688 reg |= (val << shift) & mask;
1697 u16 mask, val;
1704 &val, &shift);
1722 reg |= (val << shift) & mask;