Lines Matching refs:reg
21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
26 return mv88e6xxx_read(chip, addr, reg, val);
29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val);
37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
42 return mv88e6xxx_write(chip, addr, reg, val);
53 u16 reg;
56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
80 u16 reg;
83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
147 u16 reg;
150 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
154 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
159 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
162 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
172 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
177 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
178 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
223 u16 reg, ctrl;
274 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
278 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
283 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
285 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
289 reg |= ctrl;
291 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
300 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
301 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
424 u16 reg, ctrl;
482 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
486 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
491 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
493 reg |= ctrl;
495 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
504 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
505 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
527 u16 reg;
582 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
586 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
587 reg |= cmode;
589 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
632 u16 reg;
651 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
655 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE;
656 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE;
657 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
668 u16 reg, bits;
675 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®);
682 if ((reg & bits) == bits)
685 reg |= bits;
686 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
718 u16 reg;
720 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
724 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
732 u16 reg;
734 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
738 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
783 u16 reg;
786 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
790 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
810 reg |= state;
812 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
826 u16 reg;
828 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
832 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
836 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
839 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
842 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
845 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
851 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
858 u16 reg;
860 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
864 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
868 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
871 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
877 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
884 u16 reg;
886 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
890 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
894 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
897 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
900 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
903 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
909 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
916 u16 reg;
918 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
923 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
925 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
927 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
934 u16 reg;
936 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
941 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
943 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
945 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
952 u16 reg;
954 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
959 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
961 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
963 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1012 u16 reg;
1015 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1019 reg &= ~mask;
1020 reg |= map & mask;
1022 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1034 u16 reg;
1037 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1038 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1042 *fid = (reg & 0xf000) >> 12;
1044 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1047 ®);
1051 *fid |= (reg & upper_mask) << 4;
1060 u16 reg;
1066 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1067 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1071 reg &= 0x0fff;
1072 reg |= (fid & 0x000f) << 12;
1074 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1078 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1081 ®);
1085 reg &= ~upper_mask;
1086 reg |= (fid >> 4) & upper_mask;
1089 reg);
1103 u16 reg;
1107 ®);
1111 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1118 u16 reg;
1122 ®);
1126 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1127 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1130 reg);
1152 u16 reg;
1154 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1159 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1161 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1163 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1170 u16 reg;
1172 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1176 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1177 reg |= upstream_port;
1179 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1187 u16 reg;
1191 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1208 reg &= ~bit;
1210 reg |= bit;
1212 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1222 u16 reg;
1225 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
1229 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK;
1231 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK;
1233 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1237 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®);
1241 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1243 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1245 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg);
1251 u16 reg;
1254 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1258 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1259 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1261 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1294 u16 reg;
1297 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1302 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1304 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA;
1306 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1312 u16 reg;
1317 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1321 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1324 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1326 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1328 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1332 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1354 u16 reg, mask;
1358 ®);
1363 reg &= ~mask;
1364 reg |= pav & mask;
1367 reg);
1389 u16 reg;
1398 ®);
1402 *data = reg;
1410 u16 reg;
1412 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data;
1415 reg);
1565 u16 reg;
1567 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1572 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1674 u16 reg, mask, val;
1683 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®);
1687 reg &= ~mask;
1688 reg |= (val << shift) & mask;
1690 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
1701 u8 reg;
1717 err = mv88e6393x_port_policy_read(chip, port, ptr, ®);
1721 reg &= ~mask;
1722 reg |= (val << shift) & mask;
1724 return mv88e6393x_port_policy_write(chip, port, ptr, reg);