Lines Matching refs:port
18 #include "port.h"
21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
24 int addr = chip->info->port_base_addr + port;
29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
32 int addr = chip->info->port_base_addr + port;
37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
40 int addr = chip->info->port_base_addr + port;
50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
121 if (port < 5)
124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
130 if (port != 0)
133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
136 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
139 if (port != 2 && port != 5 && port != 6)
142 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
145 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
150 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
172 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
176 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
183 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
195 err = ops->port_set_link(chip, port, link);
200 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
214 err = ops->port_set_link(chip, port, link);
220 int port, int speed, bool alt_bit,
274 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
291 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
296 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
298 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
299 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
307 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
313 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
318 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
324 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
329 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
335 if (speed == 200 && port != 0)
338 if (speed == 2500 && port < 5)
341 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true,
346 int port)
348 if (port == 5)
355 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
361 if (speed == 200 && port < 5)
364 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false,
369 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
375 if (speed == 200 && port != 0)
378 if (speed == 2500 && port < 9)
381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
386 int port)
388 if (port == 9 || port == 10)
395 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
398 if (speed == 200 && port != 0)
401 if (speed >= 2500 && port < 9)
404 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
409 int port)
411 if (port == 9 || port == 10)
421 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
431 if (speed == 200 && port != 0)
434 if (speed >= 2500 && port > 0 && port < 9)
482 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
495 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
500 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
502 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
503 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
511 int port)
514 if (port != 0 && port != 9 && port != 10)
523 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
576 if (cmode == chip->ports[port].cmode && !force)
579 chip->ports[port].cmode = 0;
582 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
589 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
593 chip->ports[port].cmode = cmode;
599 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
602 if (port != 9 && port != 10)
605 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
608 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
611 if (port != 9 && port != 10)
625 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
628 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
634 if (port != 0 && port != 9 && port != 10)
637 if (port == 9 || port == 10) {
651 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
657 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
661 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
665 int port)
670 if (port != 5)
673 addr = chip->info->port_base_addr + port;
689 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
694 if (port != 5)
708 err = mv88e6341_port_set_cmode_writable(chip, port);
712 return mv88e6xxx_port_set_cmode(chip, port, mode, true);
715 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
720 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
729 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
734 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
745 * Do not limit the period of time that this port can be paused for by
746 * the remote end or the period of time that this port can pause the
749 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
752 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
756 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
761 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
767 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
781 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
786 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
812 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
816 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
822 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
828 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
851 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
854 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
860 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
877 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
880 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
886 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
909 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
913 int port, bool unicast)
918 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
927 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
930 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
936 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
945 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
948 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
954 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
963 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
968 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
974 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
983 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
986 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
992 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
1004 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
1009 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
1015 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1022 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1026 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
1031 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
1038 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1046 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1057 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
1067 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1074 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1080 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1088 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
1094 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
1101 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
1106 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1116 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1121 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1129 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1134 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1149 int port, bool multicast)
1154 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1163 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1166 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1172 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1179 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1182 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1191 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1198 mirror_port = &chip->ports[port].mirror_ingress;
1202 mirror_port = &chip->ports[port].mirror_egress;
1212 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1219 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
1225 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
1233 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1237 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®);
1245 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg);
1248 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1254 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1261 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1265 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1271 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
1277 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old);
1289 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new);
1292 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map)
1297 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1306 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1309 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1317 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1332 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1337 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1339 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1343 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1345 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1351 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
1357 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1366 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1372 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1374 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1379 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1381 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1386 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port,
1392 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1397 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1407 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port,
1414 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1421 int err, port;
1423 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1424 if (dsa_is_unused_port(chip->ds, port))
1427 err = mv88e6393x_port_policy_write(chip, port, pointer, data);
1437 int port)
1445 err = mv88e6393x_port_policy_write_all(chip, ptr, port);
1451 err = mv88e6xxx_g2_write(chip, ptr, port);
1460 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1467 return mv88e6393x_port_policy_write(chip, port, ptr, data);
1504 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port)
1508 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0);
1513 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1519 err = mv88e6393x_port_epc_wait_ready(chip, port);
1523 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype);
1531 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
1536 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1539 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1546 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1551 err = mv88e6xxx_port_write(chip, port,
1557 return mv88e6xxx_port_write(chip, port,
1563 int port, u16 table, u8 ptr, u16 data)
1571 return mv88e6xxx_port_write(chip, port,
1575 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1582 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1588 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1593 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1598 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1670 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1683 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®);
1690 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
1693 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1717 err = mv88e6393x_port_policy_read(chip, port, ptr, ®);
1724 return mv88e6393x_port_policy_write(chip, port, ptr, reg);