Lines Matching refs:chip
15 #include "chip.h"
19 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val);
24 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val);
29 int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
32 return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg,
38 static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src)
41 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SRC, src);
46 static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask)
48 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask);
53 static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x)
55 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, en2x);
60 static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x)
62 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X, en0x);
67 static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip,
73 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val);
82 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val);
85 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
92 err = mv88e6xxx_g2_mgmt_enable_0x(chip, 0xffff);
96 return mv88e6xxx_g2_switch_mgmt_rsvd2cpu(chip, true);
99 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
106 err = mv88e6xxx_g2_mgmt_enable_2x(chip, 0xffff);
110 return mv88e6185_g2_mgmt_rsvd2cpu(chip);
115 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
123 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_DEVICE_MAPPING,
129 int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
132 u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
137 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_TRUNK_MASK,
143 int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
146 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
149 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_TRUNK_MAPPING,
153 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
155 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
160 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
167 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
179 static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
183 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_IRL_CMD, bit, 0);
186 static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
191 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD,
197 return mv88e6xxx_g2_irl_wait(chip);
200 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
202 return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port,
206 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
208 return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port,
212 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
213 * Offset 0x0C: Cross-chip Port VLAN Data Register
216 static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
220 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_PVT_ADDR, bit, 0);
223 static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
228 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT
235 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op);
239 return mv88e6xxx_g2_pvt_op_wait(chip);
242 int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev,
247 err = mv88e6xxx_g2_pvt_op_wait(chip);
251 err = mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
256 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_PVT_DATA, data);
259 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
264 err = mv88e6xxx_g2_pvt_op_wait(chip);
268 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data);
272 return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
278 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
283 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MAC,
287 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
292 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
302 int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin)
304 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_ATU_STATS,
308 int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats)
310 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_ATU_STATS, stats);
315 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
320 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PRIO_OVERRIDE,
324 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
330 err = mv88e6xxx_g2_pot_write(chip, i, 0);
343 int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
348 err = mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_EEPROM_CMD, bit, 0);
354 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_EEPROM_CMD, bit, 0);
357 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
361 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD,
366 return mv88e6xxx_g2_eeprom_wait(chip);
369 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
375 err = mv88e6xxx_g2_eeprom_wait(chip);
379 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
383 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
387 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd);
396 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
403 err = mv88e6xxx_g2_eeprom_wait(chip);
407 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
411 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
414 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
420 err = mv88e6xxx_g2_eeprom_wait(chip);
424 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
428 return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data);
431 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
437 err = mv88e6xxx_g2_eeprom_wait(chip);
441 err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data);
445 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
448 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
458 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
471 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
481 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
494 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
505 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
517 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
530 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
544 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
553 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val);
563 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
569 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
582 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
592 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
598 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
614 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
618 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_SMI_PHY_CMD, bit, 0);
621 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
625 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD,
630 return mv88e6xxx_g2_smi_phy_wait(chip);
633 static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
653 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
656 static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
660 return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg);
664 static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
671 err = mv88e6xxx_g2_smi_phy_wait(chip);
675 err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
679 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
683 static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
690 err = mv88e6xxx_g2_smi_phy_wait(chip);
694 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
698 return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
701 static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
705 return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev);
709 static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
716 err = mv88e6xxx_g2_smi_phy_wait(chip);
720 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr);
724 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
728 static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
735 err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
739 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
742 static int _mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
748 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, devad,
753 return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, devad,
758 static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
765 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
769 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
772 static int _mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
778 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, devad,
783 return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, devad,
787 int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip,
794 return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
798 int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
805 return _mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, devad, reg,
809 int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip,
816 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
820 int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
827 return _mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, devad, reg,
832 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
836 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
838 dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
843 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
847 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
852 mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg);
855 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
857 return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL,
869 static void mv88e6250_watchdog_free(struct mv88e6xxx_chip *chip)
873 mv88e6xxx_g2_read(chip, MV88E6250_G2_WDOG_CTL, ®);
878 mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, reg);
881 static int mv88e6250_watchdog_setup(struct mv88e6xxx_chip *chip)
883 return mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL,
895 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
897 return mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
906 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
910 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
912 mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
914 dev_info(chip->dev, "Watchdog event: 0x%04x",
917 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
919 mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
921 dev_info(chip->dev, "Watchdog history: 0x%04x",
925 if (chip->info->ops->reset)
926 chip->info->ops->reset(chip);
928 mv88e6390_watchdog_setup(chip);
933 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
935 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
946 static int mv88e6393x_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
948 mv88e6390_watchdog_action(chip, irq);
953 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
968 struct mv88e6xxx_chip *chip = dev_id;
971 mv88e6xxx_reg_lock(chip);
972 if (chip->info->ops->watchdog_ops->irq_action)
973 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
974 mv88e6xxx_reg_unlock(chip);
979 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
981 mv88e6xxx_reg_lock(chip);
982 if (chip->info->ops->watchdog_ops->irq_free)
983 chip->info->ops->watchdog_ops->irq_free(chip);
984 mv88e6xxx_reg_unlock(chip);
986 free_irq(chip->watchdog_irq, chip);
987 irq_dispose_mapping(chip->watchdog_irq);
990 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
994 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
996 if (chip->watchdog_irq < 0)
997 return chip->watchdog_irq;
999 snprintf(chip->watchdog_irq_name, sizeof(chip->watchdog_irq_name),
1000 "mv88e6xxx-%s-watchdog", dev_name(chip->dev));
1002 err = request_threaded_irq(chip->watchdog_irq, NULL,
1005 chip->watchdog_irq_name, chip);
1009 mv88e6xxx_reg_lock(chip);
1010 if (chip->info->ops->watchdog_ops->irq_setup)
1011 err = chip->info->ops->watchdog_ops->irq_setup(chip);
1012 mv88e6xxx_reg_unlock(chip);
1019 static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
1025 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
1034 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
1037 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
1039 return mv88e6xxx_g2_misc_5_bit_port(chip, false);
1044 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1047 chip->g2_irq.masked |= (1 << n);
1052 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1055 chip->g2_irq.masked &= ~(1 << n);
1060 struct mv88e6xxx_chip *chip = dev_id;
1067 mv88e6xxx_reg_lock(chip);
1068 err = mv88e6xxx_g2_int_source(chip, ®);
1069 mv88e6xxx_reg_unlock(chip);
1075 sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
1086 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1088 mv88e6xxx_reg_lock(chip);
1093 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1096 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
1098 dev_err(chip->dev, "failed to mask interrupts\n");
1100 mv88e6xxx_reg_unlock(chip);
1115 struct mv88e6xxx_chip *chip = d->host_data;
1118 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
1129 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
1133 mv88e6xxx_g2_watchdog_free(chip);
1135 free_irq(chip->device_irq, chip);
1136 irq_dispose_mapping(chip->device_irq);
1139 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1143 irq_domain_remove(chip->g2_irq.domain);
1146 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
1150 chip->g2_irq.masked = ~0;
1151 mv88e6xxx_reg_lock(chip);
1152 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
1153 mv88e6xxx_reg_unlock(chip);
1157 chip->g2_irq.domain = irq_domain_add_simple(
1158 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
1159 if (!chip->g2_irq.domain)
1163 irq_create_mapping(chip->g2_irq.domain, irq);
1165 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
1167 chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
1169 if (chip->device_irq < 0) {
1170 err = chip->device_irq;
1174 snprintf(chip->device_irq_name, sizeof(chip->device_irq_name),
1175 "mv88e6xxx-%s-g2", dev_name(chip->dev));
1177 err = request_threaded_irq(chip->device_irq, NULL,
1179 IRQF_ONESHOT, chip->device_irq_name, chip);
1183 return mv88e6xxx_g2_watchdog_setup(chip);
1187 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1191 irq_domain_remove(chip->g2_irq.domain);
1196 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
1199 int phy_start = chip->info->internal_phys_offset;
1200 int phy_end = chip->info->internal_phys_offset +
1201 chip->info->num_internal_phys;
1205 irq = irq_find_mapping(chip->g2_irq.domain, phy);
1209 bus->irq[chip->info->phy_base_addr + phy] = irq;
1214 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,