Lines Matching refs:chip
13 #include "chip.h"
20 static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid)
22 return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff);
27 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all)
32 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
41 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
44 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
47 const unsigned int coeff = chip->info->age_time_coeff;
60 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
68 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
72 dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time,
78 int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
83 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
92 int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
100 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
107 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
112 static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip)
116 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_ATU_OP, bit, 0);
119 static int mv88e6xxx_g1_read_atu_violation(struct mv88e6xxx_chip *chip)
123 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP,
129 return mv88e6xxx_g1_atu_op_wait(chip);
132 static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
138 if (mv88e6xxx_num_databases(chip) > 256) {
139 err = mv88e6xxx_g1_atu_fid_write(chip, fid);
143 if (mv88e6xxx_num_databases(chip) > 64) {
145 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL,
151 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL,
155 } else if (mv88e6xxx_num_databases(chip) > 16) {
164 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP,
169 return mv88e6xxx_g1_atu_op_wait(chip);
172 int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid)
174 return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
177 static int mv88e6xxx_g1_atu_fid_read(struct mv88e6xxx_chip *chip, u16 *fid)
182 if (mv88e6xxx_num_databases(chip) > 256) {
183 err = mv88e6xxx_g1_read(chip, MV88E6352_G1_ATU_FID, &val);
188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &op);
191 if (mv88e6xxx_num_databases(chip) > 64) {
193 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL,
199 } else if (mv88e6xxx_num_databases(chip) > 16) {
214 static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip,
220 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val);
227 entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip);
233 static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip,
242 data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4;
245 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data);
253 static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip,
260 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val);
271 static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip,
279 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val);
289 int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
294 err = mv88e6xxx_g1_atu_op_wait(chip);
300 err = mv88e6xxx_g1_atu_mac_write(chip, entry);
305 err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
309 err = mv88e6xxx_g1_atu_data_read(chip, entry);
313 return mv88e6xxx_g1_atu_mac_read(chip, entry);
316 int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
321 err = mv88e6xxx_g1_atu_op_wait(chip);
325 err = mv88e6xxx_g1_atu_mac_write(chip, entry);
329 err = mv88e6xxx_g1_atu_data_write(chip, entry);
333 return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB);
336 static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid,
343 err = mv88e6xxx_g1_atu_op_wait(chip);
347 err = mv88e6xxx_g1_atu_data_write(chip, entry);
361 return mv88e6xxx_g1_atu_op(chip, fid, op);
364 int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all)
370 return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
373 static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
380 if (!chip->info->atu_move_port_mask)
383 mask = chip->info->atu_move_port_mask;
390 return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
393 int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
397 int to_port = chip->info->atu_move_port_mask;
399 return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all);
404 struct mv88e6xxx_chip *chip = dev_id;
409 mv88e6xxx_reg_lock(chip);
411 err = mv88e6xxx_g1_read_atu_violation(chip);
415 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val);
419 err = mv88e6xxx_g1_atu_fid_read(chip, &fid);
423 err = mv88e6xxx_g1_atu_data_read(chip, &entry);
427 err = mv88e6xxx_g1_atu_mac_read(chip, &entry);
431 mv88e6xxx_reg_unlock(chip);
436 trace_mv88e6xxx_atu_member_violation(chip->dev, spid,
439 chip->ports[spid].atu_member_violation++;
443 trace_mv88e6xxx_atu_miss_violation(chip->dev, spid,
446 chip->ports[spid].atu_miss_violation++;
448 if (fid != MV88E6XXX_FID_STANDALONE && chip->ports[spid].mab) {
449 err = mv88e6xxx_handle_miss_violation(chip, spid,
457 trace_mv88e6xxx_atu_full_violation(chip->dev, spid,
460 chip->ports[spid].atu_full_violation++;
466 mv88e6xxx_reg_unlock(chip);
469 dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n",
474 int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip)
478 chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain,
480 if (chip->atu_prob_irq < 0)
481 return chip->atu_prob_irq;
483 snprintf(chip->atu_prob_irq_name, sizeof(chip->atu_prob_irq_name),
484 "mv88e6xxx-%s-g1-atu-prob", dev_name(chip->dev));
486 err = request_threaded_irq(chip->atu_prob_irq, NULL,
488 IRQF_ONESHOT, chip->atu_prob_irq_name,
489 chip);
491 irq_dispose_mapping(chip->atu_prob_irq);
496 void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip)
498 free_irq(chip->atu_prob_irq, chip);
499 irq_dispose_mapping(chip->atu_prob_irq);