Lines Matching defs:port
28 /* PVT limits for 4-bit port and 5-bit switch */
175 * port 0, 1 means internal PHYs range starts at port 1, etc
266 int port;
277 int port;
413 /* Per-port timestamping resources. */
416 /* Array of port structures. */
449 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
485 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
496 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
498 /* Synchronise the port link state with that of the SERDES
500 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
506 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
520 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
525 int port);
527 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
529 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
533 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
535 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
537 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
539 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
541 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
544 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
545 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
547 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
548 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
549 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
554 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
556 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
558 /* Some devices have a per port register indicating what is
559 * the upstream port this port should forward to.
561 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
564 /* Snapshot the statistics for a port. The statistics can then
567 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
577 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
579 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
582 int port);
587 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
594 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
598 int port);
601 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
602 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
604 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
608 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
609 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
613 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port,
645 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
682 /* Access port-scoped Precision Time Protocol registers */
683 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
685 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
706 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
707 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
710 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port);
723 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port);
724 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port);
725 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port,
793 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
795 return (chip->info->invalid_port_mask & BIT(port)) != 0;
799 int port, bool mab)
801 chip->ports[port].mab = mab;