Lines Matching defs:ops
421 if (chip->info->ops->port_set_rgmii_delay) {
422 err = chip->info->ops->port_set_rgmii_delay(chip, port,
428 if (chip->info->ops->port_set_cmode) {
429 err = chip->info->ops->port_set_cmode(chip, port,
444 if (!chip->info->ops->port_set_link)
448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
452 if (chip->info->ops->port_set_speed_duplex) {
453 err = chip->info->ops->port_set_speed_duplex(chip, port,
459 if (chip->info->ops->port_set_pause) {
460 err = chip->info->ops->port_set_pause(chip, port, pause);
467 if (chip->info->ops->port_set_link(chip, port, link))
781 chip->info->ops->phylink_get_caps(chip, port, config);
800 if (chip->info->ops->pcs_ops)
801 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
819 chip->info->ops->port_set_link) {
821 err = chip->info->ops->port_set_link(chip, port,
866 if (chip->info->ops->port_set_link &&
870 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
884 const struct mv88e6xxx_ops *ops;
887 ops = chip->info->ops;
894 mode == MLO_AN_FIXED) && ops->port_sync_link)
895 err = ops->port_sync_link(chip, port, mode, false);
897 if (!err && ops->port_set_speed_duplex)
898 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
914 const struct mv88e6xxx_ops *ops;
917 ops = chip->info->ops;
926 if (ops->port_set_speed_duplex) {
927 err = ops->port_set_speed_duplex(chip, port,
933 if (ops->port_sync_link)
934 err = ops->port_sync_link(chip, port, mode, true);
946 if (!chip->info->ops->stats_snapshot)
949 return chip->info->ops->stats_snapshot(chip, port);
1122 if (chip->info->ops->stats_get_strings)
1123 count = chip->info->ops->stats_get_strings(chip, data);
1125 if (chip->info->ops->serdes_get_strings) {
1127 count = chip->info->ops->serdes_get_strings(chip, port, data);
1177 if (chip->info->ops->stats_get_sset_count)
1178 count = chip->info->ops->stats_get_sset_count(chip);
1182 if (chip->info->ops->serdes_get_sset_count)
1183 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1268 if (chip->info->ops->stats_get_stats)
1269 count = chip->info->ops->stats_get_stats(chip, port, data);
1272 if (chip->info->ops->serdes_get_stats) {
1274 count = chip->info->ops->serdes_get_stats(chip, port, data);
1305 if (chip->info->ops->serdes_get_regs_len)
1306 len += chip->info->ops->serdes_get_regs_len(chip, port);
1333 if (chip->info->ops->serdes_get_regs)
1334 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1447 if (chip->info->ops->ieee_pri_map) {
1448 err = chip->info->ops->ieee_pri_map(chip);
1453 if (chip->info->ops->ip_pri_map) {
1454 err = chip->info->ops->ip_pri_map(chip);
1482 if (chip->info->ops->set_cascade_port) {
1484 err = chip->info->ops->set_cascade_port(chip, port);
1507 if (chip->info->ops->rmu_disable)
1508 return chip->info->ops->rmu_disable(chip);
1515 if (chip->info->ops->pot_clear)
1516 return chip->info->ops->pot_clear(chip);
1523 if (chip->info->ops->mgmt_rsvd2cpu)
1524 return chip->info->ops->mgmt_rsvd2cpu(chip);
1542 if (chip->info->ops->port_setup_message_port) {
1556 if (!chip->info->ops->irl_init_all)
1563 err = chip->info->ops->irl_init_all(chip, port);
1573 if (chip->info->ops->set_switch_mac) {
1578 return chip->info->ops->set_switch_mac(chip, addr);
1682 if (!chip->info->ops->vtu_getnext)
1688 err = chip->info->ops->vtu_getnext(chip, entry);
1708 if (!chip->info->ops->vtu_getnext)
1712 err = chip->info->ops->vtu_getnext(chip, &entry);
1730 if (!chip->info->ops->vtu_loadpurge)
1733 return chip->info->ops->vtu_loadpurge(chip, entry);
1776 if (!chip->info->ops->stu_loadpurge)
1779 return chip->info->ops->stu_loadpurge(chip, entry);
2140 if (!chip->info->ops->port_set_policy)
2174 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2955 if (chip->info->ops->reset)
2956 return chip->info->ops->reset(chip);
2973 if (chip->info->ops->get_eeprom)
2981 if (chip->info->ops->get_eeprom)
3024 if (!chip->info->ops->port_set_frame_mode)
3031 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3035 if (chip->info->ops->port_set_ether_type)
3036 return chip->info->ops->port_set_ether_type(chip, port, etype);
3092 if (chip->info->ops->port_set_ucast_flood) {
3093 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3097 if (chip->info->ops->port_set_mcast_flood) {
3098 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3112 if (!chip->info->ops->set_egress_port)
3115 err = chip->info->ops->set_egress_port(chip, direction, port);
3134 if (chip->info->ops->port_set_upstream_port) {
3135 err = chip->info->ops->port_set_upstream_port(chip, port,
3142 if (chip->info->ops->set_cpu_port) {
3143 err = chip->info->ops->set_cpu_port(chip,
3240 chip->info->ops->port_set_policy) {
3241 err = chip->info->ops->port_set_policy(chip, port,
3287 if (chip->info->ops->port_set_jumbo_size) {
3288 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3319 if (chip->info->ops->port_pause_limit) {
3320 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3325 if (chip->info->ops->port_disable_learn_limit) {
3326 err = chip->info->ops->port_disable_learn_limit(chip, port);
3331 if (chip->info->ops->port_disable_pri_override) {
3332 err = chip->info->ops->port_disable_pri_override(chip, port);
3337 if (chip->info->ops->port_tag_remap) {
3338 err = chip->info->ops->port_tag_remap(chip, port);
3343 if (chip->info->ops->port_egress_rate_limiting) {
3344 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3349 if (chip->info->ops->port_setup_message_port) {
3350 err = chip->info->ops->port_setup_message_port(chip, port);
3355 if (chip->info->ops->serdes_set_tx_amplitude) {
3363 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3394 if (chip->info->ops->port_set_jumbo_size)
3396 else if (chip->info->ops->set_max_frame_size)
3409 if (!chip->info->ops->port_set_jumbo_size &&
3410 !chip->info->ops->set_max_frame_size) {
3421 if (chip->info->ops->port_set_jumbo_size)
3422 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3423 else if (chip->info->ops->set_max_frame_size)
3424 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3448 if (chip->info->ops->stats_set_histogram) {
3449 err = chip->info->ops->stats_set_histogram(chip);
3521 if (!chip->info->ops->phy_read)
3525 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3547 if (!chip->info->ops->phy_read_c45)
3551 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3563 if (!chip->info->ops->phy_write)
3567 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3580 if (!chip->info->ops->phy_write_c45)
3584 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3747 if (chip->info->ops->setup_errata) {
3748 err = chip->info->ops->setup_errata(chip);
3755 if (chip->info->ops->port_get_cmode) {
3756 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3895 if (chip->info->ops->pcs_ops &&
3896 chip->info->ops->pcs_ops->pcs_init) {
3897 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
3911 if (chip->info->ops->pcs_ops &&
3912 chip->info->ops->pcs_ops->pcs_teardown)
3913 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
3929 if (!chip->info->ops->get_eeprom)
3933 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3950 if (!chip->info->ops->set_eeprom)
3957 err = chip->info->ops->set_eeprom(chip, eeprom, data);
5401 .ops = &mv88e6250_ops,
5421 .ops = &mv88e6250_ops,
5444 .ops = &mv88e6085_ops,
5464 .ops = &mv88e6095_ops,
5488 .ops = &mv88e6097_ops,
5512 .ops = &mv88e6123_ops,
5532 .ops = &mv88e6131_ops,
5557 .ops = &mv88e6141_ops,
5582 .ops = &mv88e6161_ops,
5606 .ops = &mv88e6165_ops,
5630 .ops = &mv88e6171_ops,
5655 .ops = &mv88e6172_ops,
5679 .ops = &mv88e6175_ops,
5704 .ops = &mv88e6176_ops,
5725 .ops = &mv88e6185_ops,
5749 .ops = &mv88e6190_ops,
5773 .ops = &mv88e6190x_ops,
5797 .ops = &mv88e6191_ops,
5821 .ops = &mv88e6393x_ops,
5845 .ops = &mv88e6393x_ops,
5871 .ops = &mv88e6250_ops,
5897 .ops = &mv88e6240_ops,
5918 .ops = &mv88e6250_ops,
5942 .ops = &mv88e6290_ops,
5967 .ops = &mv88e6320_ops,
5991 .ops = &mv88e6321_ops,
6017 .ops = &mv88e6341_ops,
6041 .ops = &mv88e6350_ops,
6065 .ops = &mv88e6351_ops,
6091 .ops = &mv88e6352_ops,
6117 .ops = &mv88e6393x_ops,
6142 .ops = &mv88e6390_ops,
6167 .ops = &mv88e6390x_ops,
6191 .ops = &mv88e6393x_ops,
6443 const struct mv88e6xxx_ops *ops;
6449 ops = chip->info->ops;
6451 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6454 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6481 err = chip->info->ops->port_set_ucast_flood(chip, port,
6490 err = chip->info->ops->port_set_mcast_flood(chip, port,
6883 ds->ops = &mv88e6xxx_switch_ops;
7003 if (chip->info->ops->get_eeprom) {