Lines Matching refs:reg
61 /* RO fallback reg */
93 /* RO fallback reg */
162 u32 reg;
165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
166 reg &= ~P_TXQ_PSM_VDD(port);
167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
173 reg = core_readl(priv, CORE_SWITCH_CTRL);
174 reg |= MII_DUMB_FWDG_EN;
175 core_writel(priv, reg, CORE_SWITCH_CTRL);
180 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
182 reg |= i << (PRT_TO_QID_SHIFT * i);
183 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
189 reg = core_readl(priv, CORE_IMP_CTL);
190 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
191 reg &= ~(RX_DIS | TX_DIS);
192 core_writel(priv, reg, CORE_IMP_CTL);
194 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
195 reg &= ~(RX_DIS | TX_DIS);
196 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
205 u32 reg;
207 reg = reg_readl(priv, REG_SPHY_CNTRL);
209 reg |= PHY_RESET;
210 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
211 reg_writel(priv, reg, REG_SPHY_CNTRL);
213 reg = reg_readl(priv, REG_SPHY_CNTRL);
214 reg &= ~PHY_RESET;
216 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
217 reg_writel(priv, reg, REG_SPHY_CNTRL);
219 reg |= CK25_DIS;
221 reg_writel(priv, reg, REG_SPHY_CNTRL);
229 reg = reg_led_readl(priv, led_ctrl, 0);
230 reg |= LED_CNTRL_SPDLNK_SRC_SEL;
231 reg_led_writel(priv, reg, led_ctrl, 0);
285 u32 reg;
295 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
296 reg &= ~P_TXQ_PSM_VDD(port);
297 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
306 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
308 reg |= i << (PRT_TO_QID_SHIFT * i);
309 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
338 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
340 reg &= ~XOFF_THRESHOLD_MASK;
341 reg |= 24;
342 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
352 u32 reg;
356 reg = core_readl(priv, CORE_DIS_LEARN);
357 reg |= BIT(port);
358 core_writel(priv, reg, CORE_DIS_LEARN);
371 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
372 reg |= P_TXQ_PSM_VDD(port);
373 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
385 u32 reg;
387 reg = reg_readl(priv, REG_SWITCH_CNTRL);
388 reg |= MDIO_MASTER_SEL;
389 reg_writel(priv, reg, REG_SWITCH_CNTRL);
392 reg = 0x70;
393 reg <<= 2;
394 core_writel(priv, addr, reg);
397 reg = 0x80 << 8 | regnum << 1;
398 reg <<= 2;
401 ret = core_readl(priv, reg);
403 core_writel(priv, val, reg);
405 reg = reg_readl(priv, REG_SWITCH_CNTRL);
406 reg &= ~MDIO_MASTER_SEL;
407 reg_writel(priv, reg, REG_SWITCH_CNTRL);
476 u32 reg;
490 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
491 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
492 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
495 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
496 if (!(reg & SOFTWARE_RESET))
513 u32 reg;
518 reg = reg_readl(priv, REG_CROSSBAR);
522 reg &= ~(mask << shift);
524 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
526 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
528 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
535 reg_writel(priv, reg, REG_CROSSBAR);
537 reg = reg_readl(priv, REG_CROSSBAR);
542 (reg >> shift) & mask);
567 if (of_property_read_u32(port, "reg", &port_num))
614 int err, reg;
665 if (of_property_read_u32(child, "reg", ®) ||
666 reg >= PHY_MAX_ADDR)
669 if (!(priv->indir_phy_mask & BIT(reg)))
752 u32 reg;
780 reg = reg_readl(priv, reg_rgmii_ctrl);
781 reg &= ~ID_MODE_DIS;
782 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
784 reg |= port_mode;
786 reg |= ID_MODE_DIS;
788 reg_writel(priv, reg, reg_rgmii_ctrl);
796 u32 reg;
806 reg = reg_readl(priv, reg_rgmii_ctrl);
808 reg |= RGMII_MODE_EN;
810 reg &= ~RGMII_MODE_EN;
811 reg_writel(priv, reg, reg_rgmii_ctrl);
819 u32 reg, offset;
825 reg = core_readl(priv, offset);
826 reg &= ~LINK_STS;
827 core_writel(priv, reg, offset);
842 u32 reg, offset;
852 reg = reg_readl(priv, reg_rgmii_ctrl);
853 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
856 reg |= TX_PAUSE_EN;
858 reg |= RX_PAUSE_EN;
860 reg_writel(priv, reg, reg_rgmii_ctrl);
863 reg = LINK_STS;
866 reg |= GMII_SPEED_UP_2G;
867 reg |= MII_SW_OR;
869 reg |= SW_OVERRIDE;
874 reg |= SPDSTS_1000 << SPEED_SHIFT;
877 reg |= SPDSTS_100 << SPEED_SHIFT;
882 reg |= DUPLX_MODE;
885 reg |= TXFLOW_CNTL;
887 reg |= RXFLOW_CNTL;
889 core_writel(priv, reg, offset);
928 u32 reg;
931 reg = acb_readl(priv, ACB_CONTROL);
932 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
933 acb_writel(priv, reg, ACB_CONTROL);
934 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
935 reg |= ACB_EN | ACB_ALGORITHM;
936 acb_writel(priv, reg, ACB_CONTROL);
1074 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
1076 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1081 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1086 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1091 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1096 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1101 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1106 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1111 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1116 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1121 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1126 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1131 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1136 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1141 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1146 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1151 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1357 u32 reg, rev;
1501 reg = core_readl(priv, CORE_GMNCFGCFG);
1502 reg |= RST_MIB_CNT;
1503 core_writel(priv, reg, CORE_GMNCFGCFG);
1504 reg &= ~RST_MIB_CNT;
1505 core_writel(priv, reg, CORE_GMNCFGCFG);