Lines Matching defs:reg_base
255 ((pcie)->reg_base + (pcie)->driver_data->address_offset->block)
373 void __iomem *reg_base;
386 void __iomem *reg_base;
469 can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
488 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
491 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
502 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
504 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
518 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
534 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
555 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
566 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
568 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
569 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
577 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
579 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
600 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
601 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
603 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
604 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
606 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
615 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
616 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
636 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
640 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
657 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
663 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
699 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
774 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
776 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
782 iowrite32_rep(can->reg_base +
786 __raw_writel(data_last, can->reg_base +
790 __raw_writel(0, can->reg_base +
795 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
824 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
827 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
830 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
838 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
840 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
842 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
924 can->reg_base = KVASER_PCIEFD_KCAN_CHX_ADDR(pcie, i);
936 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
940 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
959 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
974 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
976 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1354 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1364 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1374 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
1378 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1456 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
1612 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1627 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1666 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1698 pcie->reg_base = pci_iomap(pdev, 0, 0);
1699 if (!pcie->reg_base) {
1757 pci_iounmap(pdev, pcie->reg_base);
1776 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1797 pci_iounmap(pdev, pcie->reg_base);