Lines Matching defs:txrd
65 u32 txrd; /* 0x210 */
472 priv->eskbp = grcan_read_reg(®s->txrd);
491 /* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo
495 * continue until priv->eskbp catches up to regs->txrd.
511 u32 txrd = grcan_read_reg(®s->txrd);
514 if (priv->eskbp == txrd)
528 txrd = grcan_read_reg(®s->txrd);
538 u32 txrd;
557 txrd = grcan_read_reg(®s->txrd);
558 txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size);
559 grcan_write_reg(®s->txrd, txrd);
830 u32 txrd = grcan_read_reg(®s->txrd);
844 grcan_write_reg(®s->txrd, txrd);
985 /* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */
1284 grcan_read_reg(®s->txrd) == txwr) {
1304 * then the interrupt handler increases txrd on TXLOSS,
1323 * regs->txrd - the next slot for the device to read data
1329 * The device sends messages until regs->txrd reaches regs->txwr
1332 * priv->eskbp reaches regs->txrd
1341 u32 id, txwr, txrd, space, txctrl;
1415 * in the same clock cycle as the controller updates txrd to
1419 txrd = grcan_read_reg(®s->txrd);
1420 if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) {