Lines Matching refs:params

81 	const struct spansion_nor_params *priv_params = nor->params->priv;
101 struct spi_nor_flash_parameter *params = nor->params;
103 CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr,
108 op.dummy.nbytes = params->rdsr_dummy;
143 struct spi_nor_flash_parameter *params = nor->params;
148 for (i = 0; i < params->n_dice; i++) {
149 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_STR1;
165 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
198 CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes,
206 const struct spi_nor_flash_parameter *params = nor->params;
211 for (i = 0; i < params->n_dice; i++) {
212 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2;
217 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5;
256 const struct spi_nor_flash_parameter *params = nor->params;
261 for (i = 0; i < params->n_dice; i++) {
262 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5;
284 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
342 struct spi_nor_flash_parameter *params = nor->params;
347 for (i = 0; i < params->n_dice; i++) {
348 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1;
462 nor->params->addr_nbytes = addr_mode;
463 nor->params->addr_mode_nbytes = addr_mode;
481 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes,
483 struct spi_nor_flash_parameter *params = nor->params;
491 params->page_size = 256;
492 for (i = 0; i < params->n_dice; i++) {
493 op.addr.val = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR3;
503 params->page_size = 512;
515 nor->params->writesize = 16;
533 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes,
549 struct spi_nor_flash_parameter *params = nor->params;
556 params->vreg_offset = devm_kmalloc(nor->dev, sizeof(u32), GFP_KERNEL);
557 if (!params->vreg_offset)
560 params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG;
561 params->n_dice = 1;
564 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
565 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
597 nor->params->quad_enable = cypress_nor_quad_enable_volatile;
604 struct spi_nor_flash_parameter *params = nor->params;
605 struct spi_nor_erase_type *erase_type = params->erase_map.erase_type;
608 if (!params->n_dice || !params->vreg_offset) {
615 if (params->size == SZ_256M)
616 params->n_dice = 2;
640 struct spi_nor_flash_parameter *params = nor->params;
643 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
644 params->ready = cypress_nor_sr_ready_and_clear;
674 struct spi_nor_flash_parameter *params = nor->params;
676 if (!params->n_dice || !params->vreg_offset) {
683 if (params->size == SZ_256M)
684 params->n_dice = 2;
690 if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
691 params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
695 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
701 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
709 params->rdsr_addr_nbytes = 4;
723 struct spi_nor_flash_parameter *params = nor->params;
725 params->set_octal_dtr = cypress_nor_set_octal_dtr;
726 params->ready = cypress_nor_sr_ready_and_clear;
749 nor->params->page_size = 256;
951 struct spi_nor_flash_parameter *params = nor->params;
955 if (params->size > SZ_16M) {
973 params->priv = priv_params;
974 params->ready = spansion_nor_sr_ready_and_clear;