Lines Matching refs:reg
105 u32 reg;
107 return readl_poll_timeout(host->regbase + FMC_INT, reg,
108 (reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
139 u32 reg;
141 reg = TIMING_CFG_TCSH(CS_HOLD_TIME)
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG);
184 u32 reg;
186 reg = FMC_CMD_CMD1(opcode);
187 writel(reg, host->regbase + FMC_CMD);
189 reg = FMC_DATA_NUM_CNT(len);
190 writel(reg, host->regbase + FMC_DATA_NUM);
192 reg = OP_CFG_FM_CS(priv->chipselect);
193 writel(reg, host->regbase + FMC_OP_CFG);
196 reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype;
197 writel(reg, host->regbase + FMC_OP);
235 u32 reg;
237 reg = readl(host->regbase + FMC_CFG);
238 reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK);
239 reg |= FMC_CFG_OP_MODE_NORMAL;
240 reg |= (nor->addr_nbytes == 4) ? SPI_NOR_ADDR_MODE_4BYTES
242 writel(reg, host->regbase + FMC_CFG);
248 reg = OP_CFG_FM_CS(priv->chipselect);
253 reg |= OP_CFG_MEM_IF_TYPE(if_type);
255 reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3);
256 writel(reg, host->regbase + FMC_OP_CFG);
259 reg = OP_CTRL_RW_OP(op_type) | OP_CTRL_DMA_OP_READY;
260 reg |= (op_type == FMC_OP_READ)
263 writel(reg, host->regbase + FMC_OP_DMA);
353 ret = of_property_read_u32(np, "reg", &priv->chipselect);
355 dev_err(dev, "There's no reg property for %pOF\n",