Lines Matching refs:ctrl

253 	struct tegra_nand_controller *ctrl = data;
256 isr = readl_relaxed(ctrl->regs + ISR);
257 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL);
258 dev_dbg(ctrl->dev, "isr %08x\n", isr);
269 ctrl->last_read_error = true;
272 complete(&ctrl->command_complete);
275 dev_err(ctrl->dev, "FIFO underrun\n");
278 dev_err(ctrl->dev, "FIFO overrun\n");
282 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL);
283 complete(&ctrl->dma_complete);
287 writel_relaxed(isr, ctrl->regs + ISR);
311 static void tegra_nand_dump_reg(struct tegra_nand_controller *ctrl)
316 dev_err(ctrl->dev, "Tegra NAND controller register dump\n");
323 reg = readl_relaxed(ctrl->regs + (i * 4));
324 dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg);
328 static void tegra_nand_controller_abort(struct tegra_nand_controller *ctrl)
332 disable_irq(ctrl->irq);
335 writel_relaxed(0, ctrl->regs + DMA_MST_CTRL);
336 writel_relaxed(0, ctrl->regs + COMMAND);
339 isr = readl_relaxed(ctrl->regs + ISR);
340 writel_relaxed(isr, ctrl->regs + ISR);
341 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL);
342 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL);
344 reinit_completion(&ctrl->command_complete);
345 reinit_completion(&ctrl->dma_complete);
347 enable_irq(ctrl->irq);
355 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
373 ctrl->regs + CMD_REG1);
377 ctrl->regs + CMD_REG2);
394 writel_relaxed(addr1, ctrl->regs + ADDR_REG1);
395 writel_relaxed(addr2, ctrl->regs + ADDR_REG2);
416 writel_relaxed(reg, ctrl->regs + RESP);
425 cmd |= COMMAND_GO | COMMAND_CE(ctrl->cur_cs);
426 writel_relaxed(cmd, ctrl->regs + COMMAND);
427 ret = wait_for_completion_timeout(&ctrl->command_complete,
430 dev_err(ctrl->dev, "COMMAND timeout\n");
431 tegra_nand_dump_reg(ctrl);
432 tegra_nand_controller_abort(ctrl);
437 reg = readl_relaxed(ctrl->regs + RESP);
464 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
466 ctrl->cur_cs = nand->cs[die_nr];
480 static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
486 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG);
488 writel_relaxed(0, ctrl->regs + BCH_CONFIG);
491 writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG);
493 writel_relaxed(nand->config, ctrl->regs + CONFIG);
500 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
509 writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1);
510 writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2);
512 writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1);
513 writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2);
522 writel_relaxed(addr1, ctrl->regs + ADDR_REG1);
525 writel_relaxed(page >> 16, ctrl->regs + ADDR_REG2);
532 dma_addr = dma_map_single(ctrl->dev, buf, mtd->writesize, dir);
533 ret = dma_mapping_error(ctrl->dev, dma_addr);
535 dev_err(ctrl->dev, "dma mapping error\n");
539 writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
540 writel_relaxed(dma_addr, ctrl->regs + DATA_PTR);
544 dma_addr_oob = dma_map_single(ctrl->dev, oob_buf, mtd->oobsize,
546 ret = dma_mapping_error(ctrl->dev, dma_addr_oob);
548 dev_err(ctrl->dev, "dma mapping error\n");
553 writel_relaxed(oob_len - 1, ctrl->regs + DMA_CFG_B);
554 writel_relaxed(dma_addr_oob, ctrl->regs + TAG_PTR);
571 writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL);
574 COMMAND_CE(ctrl->cur_cs);
586 writel_relaxed(cmd, ctrl->regs + COMMAND);
588 ret = wait_for_completion_timeout(&ctrl->command_complete,
591 dev_err(ctrl->dev, "COMMAND timeout\n");
592 tegra_nand_dump_reg(ctrl);
593 tegra_nand_controller_abort(ctrl);
598 ret = wait_for_completion_timeout(&ctrl->dma_complete,
601 dev_err(ctrl->dev, "DMA timeout\n");
602 tegra_nand_dump_reg(ctrl);
603 tegra_nand_controller_abort(ctrl);
611 dma_unmap_single(ctrl->dev, dma_addr_oob, mtd->oobsize, dir);
614 dma_unmap_single(ctrl->dev, dma_addr, mtd->writesize, dir);
659 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
666 tegra_nand_hw_ecc(ctrl, chip, true);
668 tegra_nand_hw_ecc(ctrl, chip, false);
673 if (!ctrl->last_read_error)
685 ctrl->last_read_error = false;
686 dec_stat = readl_relaxed(ctrl->regs + DEC_STAT_BUF);
769 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
773 tegra_nand_hw_ecc(ctrl, chip, true);
776 tegra_nand_hw_ecc(ctrl, chip, false);
781 static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl,
788 unsigned int rate = clk_get_rate(ctrl->clk) / 1000000;
811 writel_relaxed(reg, ctrl->regs + TIMING_1);
816 writel_relaxed(reg, ctrl->regs + TIMING_2);
822 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
832 tegra_nand_setup_timing(ctrl, timings);
916 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
931 dev_err(ctrl->dev, "Unsupported step size %d\n",
954 dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n");
961 dev_err(ctrl->dev,
990 dev_err(ctrl->dev, "ECC strength %d not supported\n",
1013 dev_err(ctrl->dev, "ECC strength %d not supported\n",
1019 dev_err(ctrl->dev, "ECC algorithm not supported\n");
1023 dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n",
1046 dev_err(ctrl->dev, "Unsupported writesize %d\n",
1056 writel_relaxed(nand->config, ctrl->regs + CONFIG);
1068 struct tegra_nand_controller *ctrl)
1114 chip->controller = &ctrl->controller;
1141 ctrl->chip = chip;
1149 struct tegra_nand_controller *ctrl;
1152 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
1153 if (!ctrl)
1156 ctrl->dev = &pdev->dev;
1157 platform_set_drvdata(pdev, ctrl);
1158 nand_controller_init(&ctrl->controller);
1159 ctrl->controller.ops = &tegra_nand_controller_ops;
1161 ctrl->regs = devm_platform_ioremap_resource(pdev, 0);
1162 if (IS_ERR(ctrl->regs))
1163 return PTR_ERR(ctrl->regs);
1169 ctrl->clk = devm_clk_get(&pdev->dev, "nand");
1170 if (IS_ERR(ctrl->clk))
1171 return PTR_ERR(ctrl->clk);
1188 dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
1192 writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD);
1193 writel_relaxed(HWSTATUS_MASK_DEFAULT, ctrl->regs + HWSTATUS_MASK);
1194 writel_relaxed(INT_MASK, ctrl->regs + IER);
1196 init_completion(&ctrl->command_complete);
1197 init_completion(&ctrl->dma_complete);
1199 ctrl->irq = platform_get_irq(pdev, 0);
1200 if (ctrl->irq < 0) {
1201 err = ctrl->irq;
1204 err = devm_request_irq(&pdev->dev, ctrl->irq, tegra_nand_irq, 0,
1205 dev_name(&pdev->dev), ctrl);
1207 dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err);
1211 writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL);
1213 err = tegra_nand_chips_init(ctrl->dev, ctrl);
1220 pm_runtime_put_sync_suspend(ctrl->dev);
1221 pm_runtime_force_suspend(ctrl->dev);
1229 struct tegra_nand_controller *ctrl = platform_get_drvdata(pdev);
1230 struct nand_chip *chip = ctrl->chip;
1237 pm_runtime_put_sync_suspend(ctrl->dev);
1238 pm_runtime_force_suspend(ctrl->dev);
1243 struct tegra_nand_controller *ctrl = dev_get_drvdata(dev);
1246 err = clk_prepare_enable(ctrl->clk);
1257 struct tegra_nand_controller *ctrl = dev_get_drvdata(dev);
1259 clk_disable_unprepare(ctrl->clk);