Lines Matching refs:nfc
6 * https://github.com/yuq/sunxi-nfc-mtd
262 struct sunxi_nfc *nfc = dev_id;
263 u32 st = readl(nfc->regs + NFC_REG_ST);
264 u32 ien = readl(nfc->regs + NFC_REG_INT);
270 complete(&nfc->complete);
272 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
273 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
278 static int sunxi_nfc_wait_events(struct sunxi_nfc *nfc, u32 events,
290 init_completion(&nfc->complete);
292 writel(events, nfc->regs + NFC_REG_INT);
294 ret = wait_for_completion_timeout(&nfc->complete,
301 writel(0, nfc->regs + NFC_REG_INT);
305 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
310 writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
313 dev_err(nfc->dev, "wait interrupt timedout\n");
318 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
323 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
327 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
332 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
337 writel(0, nfc->regs + NFC_REG_ECC_CTL);
338 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
340 ret = readl_poll_timeout(nfc->regs + NFC_REG_CTL, ctl,
344 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
349 static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
365 ret = dma_map_sg(nfc->dev, sg, 1, ddir);
369 if (!nfc->caps->has_mdma) {
370 dmad = dmaengine_prep_slave_sg(nfc->dmac, sg, 1, tdir, DMA_CTRL_ACK);
377 writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
378 nfc->regs + NFC_REG_CTL);
379 writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
380 writel(chunksize, nfc->regs + NFC_REG_CNT);
382 if (nfc->caps->has_mdma) {
383 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_DMA_TYPE_NORMAL,
384 nfc->regs + NFC_REG_CTL);
385 writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
386 writel(sg_dma_address(sg), nfc->regs + NFC_REG_MDMA_ADDR);
398 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
399 nfc->regs + NFC_REG_CTL);
402 dma_unmap_sg(nfc->dev, sg, 1, ddir);
406 static void sunxi_nfc_dma_op_cleanup(struct sunxi_nfc *nfc,
410 dma_unmap_sg(nfc->dev, sg, 1, ddir);
411 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
412 nfc->regs + NFC_REG_CTL);
419 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
426 ctl = readl(nfc->regs + NFC_REG_CTL) &
434 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
436 if (nfc->clk_rate != sunxi_nand->clk_rate) {
437 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
438 nfc->clk_rate = sunxi_nand->clk_rate;
441 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
442 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
443 writel(ctl, nfc->regs + NFC_REG_CTL);
449 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
460 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
464 writel(cnt, nfc->regs + NFC_REG_CNT);
466 writel(tmp, nfc->regs + NFC_REG_CMD);
472 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0);
477 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
487 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
498 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
502 writel(cnt, nfc->regs + NFC_REG_CNT);
503 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
506 writel(tmp, nfc->regs + NFC_REG_CMD);
512 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0);
625 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
626 u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
632 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
634 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
635 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
640 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
645 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
646 nfc->regs + NFC_REG_ECC_CTL);
651 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
656 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
657 nfc->regs + NFC_REG_ECC_CTL);
690 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
692 writel(sunxi_nand->ecc.ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
697 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
699 writel(0, nfc->regs + NFC_REG_ECC_CTL);
718 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
720 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
732 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
743 nfc->regs + NFC_REG_USER_DATA(step));
762 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
774 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) {
790 tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step));
802 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
816 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
822 nfc->regs + NFC_REG_CMD);
824 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
832 readl(nfc->regs + NFC_REG_ECC_ST),
846 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE,
858 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
907 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
915 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
919 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, nchunks,
929 NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
933 if (nfc->caps->has_mdma)
936 dma_async_issue_pending(nfc->dmac);
939 nfc->regs + NFC_REG_CMD);
941 ret = sunxi_nfc_wait_events(nfc, wait, false, 0);
942 if (ret && !nfc->caps->has_mdma)
943 dmaengine_terminate_all(nfc->dmac);
948 sunxi_nfc_dma_op_cleanup(nfc, DMA_FROM_DEVICE, &sg);
953 status = readl(nfc->regs + NFC_REG_ECC_ST);
1036 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1048 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1057 nfc->regs + NFC_REG_CMD);
1059 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
1280 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1288 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1292 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, ecc->steps,
1310 nfc->regs + NFC_REG_WCMD_SET);
1314 if (nfc->caps->has_mdma)
1317 dma_async_issue_pending(nfc->dmac);
1321 nfc->regs + NFC_REG_CMD);
1323 ret = sunxi_nfc_wait_events(nfc, wait, false, 0);
1324 if (ret && !nfc->caps->has_mdma)
1325 dmaengine_terminate_all(nfc->dmac);
1330 sunxi_nfc_dma_op_cleanup(nfc, DMA_TO_DEVICE, &sg);
1393 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1493 dev_err(nfc->dev, "unsupported tWB\n");
1499 dev_err(nfc->dev, "unsupported tADL\n");
1505 dev_err(nfc->dev, "unsupported tWHR\n");
1512 dev_err(nfc->dev, "unsupported tRHW\n");
1538 real_clk_rate = clk_round_rate(nfc->mod_clk, sunxi_nand->clk_rate);
1540 dev_err(nfc->dev, "Unable to round clk %lu\n",
1623 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1680 dev_err(nfc->dev, "unsupported strength\n");
1699 if (nfc->dmac || nfc->caps->has_mdma) {
1767 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1813 memcpy_toio(nfc->regs + NFC_RAM0_BASE,
1828 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1833 writel(addrs[0], nfc->regs + NFC_REG_ADDR_LOW);
1834 writel(addrs[1], nfc->regs + NFC_REG_ADDR_HIGH);
1839 nfc->regs +
1844 writel(cnt, nfc->regs + NFC_REG_CNT);
1846 writel(cmd, nfc->regs + NFC_REG_CMD);
1848 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG,
1855 memcpy_fromio(inbuf, nfc->regs + NFC_RAM0_BASE, cnt);
1920 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1926 while (!list_empty(&nfc->chips)) {
1927 sunxi_nand = list_first_entry(&nfc->chips,
1938 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1980 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1996 nand->controller = &nfc->controller;
2020 list_add_tail(&sunxi_nand->node, &nfc->chips);
2025 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
2032 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
2035 sunxi_nand_chips_cleanup(nfc);
2043 static int sunxi_nfc_dma_init(struct sunxi_nfc *nfc, struct resource *r)
2047 if (nfc->caps->has_mdma)
2050 nfc->dmac = dma_request_chan(nfc->dev, "rxtx");
2051 if (IS_ERR(nfc->dmac)) {
2052 ret = PTR_ERR(nfc->dmac);
2057 dev_warn(nfc->dev, "failed to request rxtx DMA channel: %d\n", ret);
2058 nfc->dmac = NULL;
2062 dmac_cfg.src_addr = r->start + nfc->caps->reg_io_data;
2066 dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;
2067 dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;
2068 dmaengine_slave_config(nfc->dmac, &dmac_cfg);
2077 struct sunxi_nfc *nfc;
2081 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
2082 if (!nfc)
2085 nfc->dev = dev;
2086 nand_controller_init(&nfc->controller);
2087 INIT_LIST_HEAD(&nfc->chips);
2089 nfc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
2090 if (IS_ERR(nfc->regs))
2091 return PTR_ERR(nfc->regs);
2097 nfc->ahb_clk = devm_clk_get_enabled(dev, "ahb");
2098 if (IS_ERR(nfc->ahb_clk)) {
2100 return PTR_ERR(nfc->ahb_clk);
2103 nfc->mod_clk = devm_clk_get_enabled(dev, "mod");
2104 if (IS_ERR(nfc->mod_clk)) {
2106 return PTR_ERR(nfc->mod_clk);
2109 nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
2110 if (IS_ERR(nfc->reset))
2111 return PTR_ERR(nfc->reset);
2113 ret = reset_control_deassert(nfc->reset);
2119 nfc->caps = of_device_get_match_data(&pdev->dev);
2120 if (!nfc->caps) {
2125 ret = sunxi_nfc_rst(nfc);
2129 writel(0, nfc->regs + NFC_REG_INT);
2131 0, "sunxi-nand", nfc);
2135 ret = sunxi_nfc_dma_init(nfc, r);
2140 platform_set_drvdata(pdev, nfc);
2142 ret = sunxi_nand_chips_init(dev, nfc);
2151 if (nfc->dmac)
2152 dma_release_channel(nfc->dmac);
2154 reset_control_assert(nfc->reset);
2161 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
2163 sunxi_nand_chips_cleanup(nfc);
2165 reset_control_assert(nfc->reset);
2167 if (nfc->dmac)
2168 dma_release_channel(nfc->dmac);