Lines Matching defs:timings
1394 const struct nand_sdr_timings *timings;
1399 timings = nand_get_sdr_timings(conf);
1400 if (IS_ERR(timings))
1404 if (timings->tCLS_min > min_clk_period)
1405 min_clk_period = timings->tCLS_min;
1408 if (timings->tCLH_min > min_clk_period)
1409 min_clk_period = timings->tCLH_min;
1412 if (timings->tCS_min > min_clk_period)
1413 min_clk_period = timings->tCS_min;
1416 if (timings->tCH_min > min_clk_period)
1417 min_clk_period = timings->tCH_min;
1420 if (timings->tWP_min > min_clk_period)
1421 min_clk_period = timings->tWP_min;
1424 if (timings->tWH_min > min_clk_period)
1425 min_clk_period = timings->tWH_min;
1428 if (timings->tALS_min > min_clk_period)
1429 min_clk_period = timings->tALS_min;
1432 if (timings->tDS_min > min_clk_period)
1433 min_clk_period = timings->tDS_min;
1436 if (timings->tDH_min > min_clk_period)
1437 min_clk_period = timings->tDH_min;
1440 if (timings->tRR_min > (min_clk_period * 3))
1441 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1444 if (timings->tALH_min > min_clk_period)
1445 min_clk_period = timings->tALH_min;
1448 if (timings->tRP_min > min_clk_period)
1449 min_clk_period = timings->tRP_min;
1452 if (timings->tREH_min > min_clk_period)
1453 min_clk_period = timings->tREH_min;
1456 if (timings->tRC_min > (min_clk_period * 2))
1457 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1460 if (timings->tWC_min > (min_clk_period * 2))
1461 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1464 if (timings->tWB_max > (min_clk_period * 20))
1465 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
1467 if (timings->tADL_min > (min_clk_period * 32))
1468 min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32);
1470 if (timings->tWHR_min > (min_clk_period * 32))
1471 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
1473 if (timings->tRHW_min > (min_clk_period * 20))
1474 min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
1485 * 2/ Use EDO mode (only works if timings->tRLOH > 0)
1487 if (timings->tREA_max > min_clk_period && !timings->tRLOH_min)
1488 min_clk_period = timings->tREA_max;
1490 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1497 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1503 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1509 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1549 * output cycle timings shall be used if the host drives tRC less than
1553 if (min_clk_period * 2 < 30 || min_clk_period * 1000 < timings->tREA_max)