Lines Matching defs:rnandc
216 struct rnandc {
244 static inline struct rnandc *to_rnandc(struct nand_controller *ctrl)
246 return container_of(ctrl, struct rnandc, controller);
259 static void rnandc_dis_correction(struct rnandc *rnandc)
263 control = readl_relaxed(rnandc->regs + CONTROL_REG);
265 writel_relaxed(control, rnandc->regs + CONTROL_REG);
268 static void rnandc_en_correction(struct rnandc *rnandc)
272 control = readl_relaxed(rnandc->regs + CONTROL_REG);
274 writel_relaxed(control, rnandc->regs + CONTROL_REG);
277 static void rnandc_clear_status(struct rnandc *rnandc)
279 writel_relaxed(0, rnandc->regs + INT_STATUS_REG);
280 writel_relaxed(0, rnandc->regs + ECC_STAT_REG);
281 writel_relaxed(0, rnandc->regs + ECC_CNT_REG);
284 static void rnandc_dis_interrupts(struct rnandc *rnandc)
286 writel_relaxed(0, rnandc->regs + INT_MASK_REG);
289 static void rnandc_en_interrupts(struct rnandc *rnandc, u32 val)
291 if (!rnandc->use_polling)
292 writel_relaxed(val, rnandc->regs + INT_MASK_REG);
295 static void rnandc_clear_fifo(struct rnandc *rnandc)
297 writel_relaxed(FIFO_INIT, rnandc->regs + FIFO_INIT_REG);
303 struct rnandc *rnandc = to_rnandc(chip->controller);
306 if (chip == rnandc->selected_chip && die_nr == rnand->selected_die)
309 rnandc_clear_status(rnandc);
310 writel_relaxed(MEM_CTRL_CS(cs) | MEM_CTRL_DIS_WP(cs), rnandc->regs + MEM_CTRL_REG);
311 writel_relaxed(rnand->control, rnandc->regs + CONTROL_REG);
312 writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG);
313 writel_relaxed(rnand->timings_asyn, rnandc->regs + TIMINGS_ASYN_REG);
314 writel_relaxed(rnand->tim_seq0, rnandc->regs + TIM_SEQ0_REG);
315 writel_relaxed(rnand->tim_seq1, rnandc->regs + TIM_SEQ1_REG);
316 writel_relaxed(rnand->tim_gen_seq0, rnandc->regs + TIM_GEN_SEQ0_REG);
317 writel_relaxed(rnand->tim_gen_seq1, rnandc->regs + TIM_GEN_SEQ1_REG);
318 writel_relaxed(rnand->tim_gen_seq2, rnandc->regs + TIM_GEN_SEQ2_REG);
319 writel_relaxed(rnand->tim_gen_seq3, rnandc->regs + TIM_GEN_SEQ3_REG);
321 rnandc->selected_chip = chip;
325 static void rnandc_trigger_op(struct rnandc *rnandc, struct rnandc_op *rop)
327 writel_relaxed(rop->addr0_col, rnandc->regs + ADDR0_COL_REG);
328 writel_relaxed(rop->addr0_row, rnandc->regs + ADDR0_ROW_REG);
329 writel_relaxed(rop->addr1_col, rnandc->regs + ADDR1_COL_REG);
330 writel_relaxed(rop->addr1_row, rnandc->regs + ADDR1_ROW_REG);
331 writel_relaxed(rop->ecc_offset, rnandc->regs + ECC_OFFSET_REG);
332 writel_relaxed(rop->gen_seq_ctrl, rnandc->regs + GEN_SEQ_CTRL_REG);
333 writel_relaxed(DATA_SIZE(rop->len), rnandc->regs + DATA_SIZE_REG);
334 writel_relaxed(rop->command, rnandc->regs + COMMAND_REG);
337 static void rnandc_trigger_dma(struct rnandc *rnandc)
341 DMA_CTRL_START, rnandc->regs + DMA_CTRL_REG);
346 struct rnandc *rnandc = private;
348 rnandc_dis_interrupts(rnandc);
349 complete(&rnandc->complete);
354 static int rnandc_wait_end_of_op(struct rnandc *rnandc,
362 ret = readl_poll_timeout(rnandc->regs + STATUS_REG, status,
366 dev_err(rnandc->dev, "Operation timed out, status: 0x%08x\n",
372 static int rnandc_wait_end_of_io(struct rnandc *rnandc,
378 if (rnandc->use_polling) {
383 ret = readl_poll_timeout(rnandc->regs + INT_STATUS_REG, status,
388 ret = wait_for_completion_timeout(&rnandc->complete,
402 struct rnandc *rnandc = to_rnandc(chip->controller);
421 rnandc_clear_status(rnandc);
422 reinit_completion(&rnandc->complete);
423 rnandc_en_interrupts(rnandc, INT_DMA_ENDED);
424 rnandc_en_correction(rnandc);
427 dma_addr = dma_map_single(rnandc->dev, rnandc->buf, mtd->writesize,
429 writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG);
430 writel(mtd->writesize, rnandc->regs + DMA_CNT_REG);
431 writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG);
433 rnandc_trigger_op(rnandc, &rop);
434 rnandc_trigger_dma(rnandc);
436 ret = rnandc_wait_end_of_io(rnandc, chip);
437 dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_FROM_DEVICE);
438 rnandc_dis_correction(rnandc);
440 dev_err(rnandc->dev, "Read page operation never ending\n");
444 ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG);
459 bf = nand_check_erased_ecc_chunk(rnandc->buf + off,
473 bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG));
482 memcpy(buf, rnandc->buf, mtd->writesize);
490 struct rnandc *rnandc = to_rnandc(chip->controller);
515 rnandc_clear_status(rnandc);
516 rnandc_en_correction(rnandc);
517 rnandc_trigger_op(rnandc, &rop);
519 while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
522 while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
525 ioread32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off,
528 if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) {
529 dev_err(rnandc->dev, "Clearing residual data in the read FIFO\n");
530 rnandc_clear_fifo(rnandc);
533 ret = rnandc_wait_end_of_op(rnandc, chip);
534 rnandc_dis_correction(rnandc);
536 dev_err(rnandc->dev, "Read subpage operation never ending\n");
540 ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG);
567 bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG));
582 struct rnandc *rnandc = to_rnandc(chip->controller);
597 memcpy(rnandc->buf, buf, mtd->writesize);
601 rnandc_clear_status(rnandc);
602 reinit_completion(&rnandc->complete);
603 rnandc_en_interrupts(rnandc, INT_MEM_RDY(cs));
604 rnandc_en_correction(rnandc);
607 dma_addr = dma_map_single(rnandc->dev, (void *)rnandc->buf, mtd->writesize,
609 writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG);
610 writel(mtd->writesize, rnandc->regs + DMA_CNT_REG);
611 writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG);
613 rnandc_trigger_op(rnandc, &rop);
614 rnandc_trigger_dma(rnandc);
616 ret = rnandc_wait_end_of_io(rnandc, chip);
617 dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_TO_DEVICE);
618 rnandc_dis_correction(rnandc);
620 dev_err(rnandc->dev, "Write page operation never ending\n");
635 struct rnandc *rnandc = to_rnandc(chip->controller);
655 rnandc_clear_status(rnandc);
656 rnandc_en_correction(rnandc);
657 rnandc_trigger_op(rnandc, &rop);
659 while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG)))
662 iowrite32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off,
665 while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
668 ret = rnandc_wait_end_of_op(rnandc, chip);
669 rnandc_dis_correction(rnandc);
671 dev_err(rnandc->dev, "Write subpage operation never ending\n");
685 struct rnandc *rnandc = to_rnandc(chip->controller);
835 dev_err(rnandc->dev, "Cannot handle more than one wait delay\n");
842 rnandc_trigger_op(rnandc, &rop);
847 while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
850 while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
853 ioread32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf, words);
855 last_bytes = readl_relaxed(rnandc->regs + FIFO_DATA_REG);
860 if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) {
861 dev_warn(rnandc->dev,
863 rnandc_clear_fifo(rnandc);
866 while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG)))
869 iowrite32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf,
875 writel_relaxed(last_bytes, rnandc->regs + FIFO_DATA_REG);
878 while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
882 ret = rnandc_wait_end_of_op(rnandc, chip);
893 struct rnandc *rnandc = to_rnandc(chip->controller);
894 unsigned int period_ns = 1000000000 / rnandc->ext_clk_rate;
903 dev_err(rnandc->dev, "Read and write hold times must be identical\n");
1011 struct rnandc *rnandc = to_rnandc(chip->controller);
1014 dev_err(rnandc->dev, "Unsupported page size\n");
1029 dev_err(rnandc->dev, "Unsupported ECC chunk size\n");
1059 dev_err(rnandc->dev, "Unsupported ECC strength\n");
1080 struct rnandc *rnandc = to_rnandc(chip->controller);
1089 dev_err(rnandc->dev, "No minimum ECC strength\n");
1114 struct rnandc *rnandc = to_rnandc(chip->controller);
1124 dev_err(rnandc->dev, "Small page devices not supported\n");
1144 dev_err(rnandc->dev, "Unsupported memory organization\n");
1152 dev_err(rnandc->dev, "ECC initialization failed (%d)\n", ret);
1168 static int rnandc_alloc_dma_buf(struct rnandc *rnandc,
1176 list_for_each_entry_safe(entry, temp, &rnandc->chips, node) {
1182 if (rnandc->buf && rnandc->buf_sz < max_len) {
1183 devm_kfree(rnandc->dev, rnandc->buf);
1184 rnandc->buf = NULL;
1187 if (!rnandc->buf) {
1188 rnandc->buf_sz = max_len;
1189 rnandc->buf = devm_kmalloc(rnandc->dev, max_len,
1191 if (!rnandc->buf)
1198 static int rnandc_chip_init(struct rnandc *rnandc, struct device_node *np)
1209 dev_err(rnandc->dev, "Invalid reg property (%d)\n", ret);
1214 rnand = devm_kzalloc(rnandc->dev, struct_size(rnand, sels, nsels),
1225 dev_err(rnandc->dev, "Incomplete reg property (%d)\n", ret);
1230 dev_err(rnandc->dev, "Invalid reg property (%d)\n", cs);
1234 if (test_and_set_bit(cs, &rnandc->assigned_cs)) {
1235 dev_err(rnandc->dev, "CS %d already assigned\n", cs);
1247 chip->controller = &rnandc->controller;
1251 mtd->dev.parent = rnandc->dev;
1253 dev_err(rnandc->dev, "Missing MTD label\n");
1259 dev_err(rnandc->dev, "Failed to scan the NAND chip (%d)\n", ret);
1263 ret = rnandc_alloc_dma_buf(rnandc, mtd);
1269 dev_err(rnandc->dev, "Failed to register MTD device (%d)\n", ret);
1273 list_add_tail(&rnand->node, &rnandc->chips);
1283 static void rnandc_chips_cleanup(struct rnandc *rnandc)
1289 list_for_each_entry_safe(entry, temp, &rnandc->chips, node) {
1298 static int rnandc_chips_init(struct rnandc *rnandc)
1303 for_each_child_of_node(rnandc->dev->of_node, np) {
1304 ret = rnandc_chip_init(rnandc, np);
1314 rnandc_chips_cleanup(rnandc);
1321 struct rnandc *rnandc;
1325 rnandc = devm_kzalloc(&pdev->dev, sizeof(*rnandc), GFP_KERNEL);
1326 if (!rnandc)
1329 rnandc->dev = &pdev->dev;
1330 nand_controller_init(&rnandc->controller);
1331 rnandc->controller.ops = &rnandc_ops;
1332 INIT_LIST_HEAD(&rnandc->chips);
1333 init_completion(&rnandc->complete);
1335 rnandc->regs = devm_platform_ioremap_resource(pdev, 0);
1336 if (IS_ERR(rnandc->regs))
1337 return PTR_ERR(rnandc->regs);
1351 rnandc->ext_clk_rate = clk_get_rate(eclk);
1354 rnandc_dis_interrupts(rnandc);
1361 rnandc->use_polling = true;
1364 "renesas-nand-controller", rnandc);
1373 rnandc_clear_fifo(rnandc);
1375 platform_set_drvdata(pdev, rnandc);
1377 ret = rnandc_chips_init(rnandc);
1391 struct rnandc *rnandc = platform_get_drvdata(pdev);
1393 rnandc_chips_cleanup(rnandc);