Lines Matching defs:conf_regs
128 * @conf_regs: SMC configuration registers for command phase
138 void __iomem *conf_regs;
218 nfc->conf_regs + PL35X_SMC_DIRECT_CMD);
226 writel(bw, nfc->conf_regs + PL35X_SMC_OPMODE);
235 nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR);
243 ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_MEMC_STATUS, reg,
261 ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_ECC_STATUS, reg,
278 ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG);
281 writel(ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
322 writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES);
326 writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
456 ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk));
479 ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk));
890 plnand->ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG);
893 writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
1008 nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR);
1028 nfc->conf_regs + PL35X_SMC_ECC_CMD1);
1033 nfc->conf_regs + PL35X_SMC_ECC_CMD2);
1152 nfc->conf_regs = devm_ioremap_resource(&smc_amba->dev, &smc_amba->res);
1153 if (IS_ERR(nfc->conf_regs))
1154 return PTR_ERR(nfc->conf_regs);