Lines Matching defs:mode
18 * for timing mode 0, respectively 200us and 500ns.
26 .timings.mode = 0,
71 .timings.mode = 1,
116 .timings.mode = 2,
161 .timings.mode = 3,
206 .timings.mode = 4,
251 .timings.mode = 5,
299 .timings.mode = 0,
341 .timings.mode = 1,
383 .timings.mode = 2,
425 .timings.mode = 3,
467 .timings.mode = 4,
509 .timings.mode = 5,
550 /* All NAND chips share the same reset data interface: SDR mode 0 */
557 * onfi_find_closest_sdr_mode - Derive the closest ONFI SDR timing mode given a
565 int mode;
567 for (mode = ARRAY_SIZE(onfi_sdr_timings) - 1; mode > 0; mode--) {
568 onfi_timings = &onfi_sdr_timings[mode].timings.sdr;
597 return mode;
604 * onfi_find_closest_nvddr_mode - Derive the closest ONFI NVDDR timing mode
612 int mode;
614 for (mode = ARRAY_SIZE(onfi_nvddr_timings) - 1; mode > 0; mode--) {
615 onfi_timings = &onfi_nvddr_timings[mode].timings.nvddr;
639 return mode;
647 * given ONFI mode
650 * @timing_mode: The ONFI timing mode
664 * Initialize timings that cannot be deduced from timing mode:
683 * given ONFI mode
686 * @timing_mode: The ONFI timing mode
700 * Initialize timings that cannot be deduced from timing mode:
722 * ONFI mode
726 * @timing_mode: The ONFI timing mode